Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View

Abstract

Today the task of design verification has become one of the key bottlenecks in hardware and system design. To address this topic, several verification languages, methods and tools, which address several issues of the verification process, were developed by multiple EDA vendors over the last years. This paper takes an industrial user's point of view and explores the difficulties introducing new verification methods into a company's "naturally grown" and well established design flow - taking into account application domain specific requirements, constraints given by the existing design environment and economical aspects. The presented approach extends the capabilities of an existing verification strategy by powerful new features while keeping in mind integration, reuse and applicability aspects. Based on an industrial design example the effectiveness and potential of the developed approach is shown