Discrete current limiting circuit for emerging memory programming

L. Laborie, Paola Trotti, Killian Veyret, C. Cagli
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Abstract

This work presents a novel, discrete-component circuit for the electrical characterisation of Resistive Random Access Memory (RRAM). The forming of State-Of-The-Art RRAM cell in one resistor (1R) configuration is demonstrated, enabling the possibility of sparing the commonly integrated series transistor. The presented DCL circuit is furthermore benchmarked versus other discrete and integrated typologies, showing dramatic improvement over existing discrete solutions, and comparable performances with integrated architectures. Finally, multi-bit storage is experimentally demonstrated through modulation of the programming current amplitude.
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用于新兴存储器编程的分立限流电路
这项工作提出了一种新的、离散元件电路,用于电阻性随机存取存储器(RRAM)的电气特性。演示了在一个电阻器(1R)配置中形成最先进的RRAM单元,从而可以节省通常集成的系列晶体管。所提出的DCL电路进一步与其他离散和集成类型进行了基准测试,显示出比现有离散解决方案有显着改进,并且与集成架构具有相当的性能。最后,通过调制编程电流幅度,实验证明了多比特存储。
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