Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094175
Shih-Kai Lin, T. Chang, Wei‐Chen Huang, Yung‐Fang Tan, Chen‐Hsin Lien
High resistance state (HRS) resistance on the set voltage in hafnium oxide-based resistance random access memory (RRAM) is investigated. Set voltage has a positive correlation to HRS in statistics. For analyzing the switching characteristics at different HRS resistance level, filament properties in the switching layer are analyzed by current-fitting technique. The fitting results show that Schottky distance becomes saturated at high resistance HRS. Finally, a physical model is proposed to explain our observation.
{"title":"Analysis of Critical Schottky Distance Effect and Distributed Set Voltage in HfO2-based 1T-1R Device","authors":"Shih-Kai Lin, T. Chang, Wei‐Chen Huang, Yung‐Fang Tan, Chen‐Hsin Lien","doi":"10.1109/ICMTS55420.2023.10094175","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094175","url":null,"abstract":"High resistance state (HRS) resistance on the set voltage in hafnium oxide-based resistance random access memory (RRAM) is investigated. Set voltage has a positive correlation to HRS in statistics. For analyzing the switching characteristics at different HRS resistance level, filament properties in the switching layer are analyzed by current-fitting technique. The fitting results show that Schottky distance becomes saturated at high resistance HRS. Finally, a physical model is proposed to explain our observation.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124880070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094106
K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto
Source-to-drain series resistance (RSD) of a large number of identically designed MOSFETs was extracted using a recently proposed single-device method. By examining statistical correlations with other device parameters, it was confirmed that variability of the extracted RSD values does not correspond to real series resistance variability, but is mainly caused by some non- RSD variability sources. This suggests that, for the single-device method to work, non- RSD variability needs to be reduced by averaging multiple devices, or using wide channel devices.
{"title":"Variability of MOSFET Series Resistance Extracted from Individual Devices: Is Direct Variability Measurement Possible?","authors":"K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto","doi":"10.1109/ICMTS55420.2023.10094106","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094106","url":null,"abstract":"Source-to-drain series resistance (RSD) of a large number of identically designed MOSFETs was extracted using a recently proposed single-device method. By examining statistical correlations with other device parameters, it was confirmed that variability of the extracted RSD values does not correspond to real series resistance variability, but is mainly caused by some non- RSD variability sources. This suggests that, for the single-device method to work, non- RSD variability needs to be reduced by averaging multiple devices, or using wide channel devices.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"86 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125924877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094091
Xiaorui Jie, R. V. Langevelde, K. Xia, Lei Chao, C. McAndrew, Qilin Zhang, Matthew Bacchi, Wuxia Li
Accurate modeling of the gate-drain capacitance Cgd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved Cgd model, based on the physics that the drift region under the poly-gate is fully depleted at high Vdg, and validate our model against gate charge measurements for both n-and p-type 90V LDMOS transistors.
{"title":"Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications","authors":"Xiaorui Jie, R. V. Langevelde, K. Xia, Lei Chao, C. McAndrew, Qilin Zhang, Matthew Bacchi, Wuxia Li","doi":"10.1109/ICMTS55420.2023.10094091","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094091","url":null,"abstract":"Accurate modeling of the gate-drain capacitance Cgd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved Cgd model, based on the physics that the drift region under the poly-gate is fully depleted at high Vdg, and validate our model against gate charge measurements for both n-and p-type 90V LDMOS transistors.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122094192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094065
A. A. Gruszecki, R. Prasad, S. Suryavanshi, G. Yeric, C. D. Young
Abstract-Correlated electron RAM (CeRAM) device test structures utilizing C-doped NiO were fabricated and electrically characterized to determine functionality in extreme environments. CeRAM devices were demonstrated to repeatedly cycle at temperatures up to 200°C while maintaining a substantial memory window of over 1000 x. Careful selection of compliance current when sweeping the high resistance state (OFF) is required for optimal device performance. The presence of a temperature dependent leakage current in the OFF state results in reducing OFF resistance at elevated temperatures.
{"title":"Test Methodology Development for Investigating CeRAM at Elevated Temperatures","authors":"A. A. Gruszecki, R. Prasad, S. Suryavanshi, G. Yeric, C. D. Young","doi":"10.1109/ICMTS55420.2023.10094065","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094065","url":null,"abstract":"Abstract-Correlated electron RAM (CeRAM) device test structures utilizing C-doped NiO were fabricated and electrically characterized to determine functionality in extreme environments. CeRAM devices were demonstrated to repeatedly cycle at temperatures up to 200°C while maintaining a substantial memory window of over 1000 x. Careful selection of compliance current when sweeping the high resistance state (OFF) is required for optimal device performance. The presence of a temperature dependent leakage current in the OFF state results in reducing OFF resistance at elevated temperatures.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116872799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094138
Kunyang Liu, Yichen Tang, Shufan Xu, H. Shinohara
In this paper, a method to observe random telegraph noise in a hybrid SRAM PUF array is presented. This allows low-cost observation of RTN in a number of bitcells by applying VSS bias voltages to measure their temporal mismatches. Also, the changes in RTN amplitude after hot carrier injection burn-in, which is used for PUF stabilization, have been measured and analyzed. Experimental results from a 130-nm CMOS test chip show that the average RTN amplitude across 80-run measurements increases from 1.46 mV before HCI to 9.72 mV after 18-min HCI. The maximum RTN amplitude also increases from 10.13 mV to 84.50 mV. These results indicate that RTN is not an omittable factor especially for a PUF using a hot carrier injection-based stabilization technique and should be carefully considered when deciding the burn-in strategy.
{"title":"VSS-Bias-Based Measurement of Random Telegraph Noise in Hybrid SRAM PUF after Hot Carrier Injection Burn-in","authors":"Kunyang Liu, Yichen Tang, Shufan Xu, H. Shinohara","doi":"10.1109/ICMTS55420.2023.10094138","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094138","url":null,"abstract":"In this paper, a method to observe random telegraph noise in a hybrid SRAM PUF array is presented. This allows low-cost observation of RTN in a number of bitcells by applying VSS bias voltages to measure their temporal mismatches. Also, the changes in RTN amplitude after hot carrier injection burn-in, which is used for PUF stabilization, have been measured and analyzed. Experimental results from a 130-nm CMOS test chip show that the average RTN amplitude across 80-run measurements increases from 1.46 mV before HCI to 9.72 mV after 18-min HCI. The maximum RTN amplitude also increases from 10.13 mV to 84.50 mV. These results indicate that RTN is not an omittable factor especially for a PUF using a hot carrier injection-based stabilization technique and should be carefully considered when deciding the burn-in strategy.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128337466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094101
L. Ivy, A. Lal
Advancing highly integrated micro sensors and actuators calls for the ability to scale down three-dimensional structures while ensuring efficient electrical interconnectivity. This necessitates addressing a pressing need to develop novel techniques for shrinking components and facilitating seamless interconnectivity to the miniature structures. Here, we demonstrate a three-step fabrication method to produce 3D prints fabricated by direct laser writing (DLW) via two-photon polymerization (TPP), with multisided evaporated metal patterns. The three steps consist of printing the core structure and shadow mask shell (SMS) on sacrificial Dextran 70, evaporating metal onto the desired side(s), and then releasing the core and SMS in water. To showcase this process’ capabilities, we produced a simple characterization structure featuring two electrical vias, an out-of-plane serpentine resistor, and four solderable electrodes. With this test structure, three firsts were achieved for the TPP community: (1) The deposition of metal patterns onto opposing sides of a DLW structure; (2) the flip-chip soldering of said structure to a PCB; and (3) the verification of electrical continuity through its two microvias.
{"title":"Solderable Multisided Metal Patterns Enables 3D Integrable Direct Laser Written Polymer MEMS","authors":"L. Ivy, A. Lal","doi":"10.1109/ICMTS55420.2023.10094101","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094101","url":null,"abstract":"Advancing highly integrated micro sensors and actuators calls for the ability to scale down three-dimensional structures while ensuring efficient electrical interconnectivity. This necessitates addressing a pressing need to develop novel techniques for shrinking components and facilitating seamless interconnectivity to the miniature structures. Here, we demonstrate a three-step fabrication method to produce 3D prints fabricated by direct laser writing (DLW) via two-photon polymerization (TPP), with multisided evaporated metal patterns. The three steps consist of printing the core structure and shadow mask shell (SMS) on sacrificial Dextran 70, evaporating metal onto the desired side(s), and then releasing the core and SMS in water. To showcase this process’ capabilities, we produced a simple characterization structure featuring two electrical vias, an out-of-plane serpentine resistor, and four solderable electrodes. With this test structure, three firsts were achieved for the TPP community: (1) The deposition of metal patterns onto opposing sides of a DLW structure; (2) the flip-chip soldering of said structure to a PCB; and (3) the verification of electrical continuity through its two microvias.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124352055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094178
M. Massarotto, M. Segatto, F. Driussi, A. Affanni, S. Lancaster, S. Slesazeck, T. Mikolajick, D. Esseni
Ferroelectric Tunnel Junctions (FTJs) operating as memristors are promising electron devices to realize artificial synapses for neuromorphic computing. But the understanding of their operation requires an in-depth electrical characterization. In this work, an inhouse experimental setup is employed along with novel experimental methodologies to investigate the largesignal (LS) and small-signal (AC) responses of FTJs. For the first time, our experiments and physics-based simulations help to explain the discrepancies between LS and AC experiments reported in previous literature.
{"title":"Bridging Large-Signal and Small-Signal Responses of Hafnium-Based Ferroelectric Tunnel Junctions","authors":"M. Massarotto, M. Segatto, F. Driussi, A. Affanni, S. Lancaster, S. Slesazeck, T. Mikolajick, D. Esseni","doi":"10.1109/ICMTS55420.2023.10094178","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094178","url":null,"abstract":"Ferroelectric Tunnel Junctions (FTJs) operating as memristors are promising electron devices to realize artificial synapses for neuromorphic computing. But the understanding of their operation requires an in-depth electrical characterization. In this work, an inhouse experimental setup is employed along with novel experimental methodologies to investigate the largesignal (LS) and small-signal (AC) responses of FTJs. For the first time, our experiments and physics-based simulations help to explain the discrepancies between LS and AC experiments reported in previous literature.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115930979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094137
T. Ohguro, Hideharu Kojima, T. Hara, T. Nishiwaki, Kenya Kobayashi
Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.
{"title":"Measuring of parasitic resistance of stacked chip of Si power device","authors":"T. Ohguro, Hideharu Kojima, T. Hara, T. Nishiwaki, Kenya Kobayashi","doi":"10.1109/ICMTS55420.2023.10094137","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094137","url":null,"abstract":"Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130751332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094156
Alin Panca, A. Serb, S. Stathopoulos, S. K. Garlapati, T. Prodromakis
Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-automated RRAM device testing platform.
{"title":"Automated RRAM measurements using a semi-automated probe station and ArC ONE interface","authors":"Alin Panca, A. Serb, S. Stathopoulos, S. K. Garlapati, T. Prodromakis","doi":"10.1109/ICMTS55420.2023.10094156","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094156","url":null,"abstract":"Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-automated RRAM device testing platform.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133062483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-27DOI: 10.1109/ICMTS55420.2023.10094072
Pei-Yu Wu, Xin-Ying Tsai, T. Chang, T. Tsai, S. Sze
In GaN-based metal-insulatorsemiconductor high electron mobility transistors (GaNbased MIS HEMTs), Al2O3/Si3N4 bilayer-gate insulator- MIS HEMTs (Al2O3/Si3N4-MIS HEMTs) are considered to have the advantages of low gate leakage and low interface defects. This study will compare Si3N4 gate insulator-MIS HEMTs (Si3N4-MIS HEMTs) to discuss and clarify the abnormal deterioration mechanism of Al2O3/Si3N4-MIS HEMTs under Hot Carrier Effect (HCE). Therefore, in this study, the results of HCE between Si3N4-MIS HEMTs and Al2O3/Si3N4-MIS HEMTs are compared, and the abnormal HCS degradations in Al2O3/Si3N4-MIS HEMTs are discussed and explained in depth. A series of electrical and simulation analysis is conducted in order to verify the degradation mechanism model proposed in this study.
在氮化镓基金属绝缘体半导体高电子迁移率晶体管(GaN-based MIS HEMTs)中，Al2O3/Si3N4双层栅绝缘体-MIS HEMTs (Al2O3/Si3N4-MIS HEMTs)被认为具有低栅漏和低界面缺陷的优点。本研究将比较Si3N4栅极绝缘子- mis HEMTs (Si3N4- mis HEMTs)，探讨和阐明Al2O3/Si3N4- mis HEMTs在热载子效应(HCE)下的异常劣化机理。因此，本研究比较了Si3N4-MIS HEMTs和Al2O3/Si3N4-MIS HEMTs的HCE结果，并对Al2O3/Si3N4-MIS HEMTs中HCS的异常降解进行了深入的讨论和解释。为了验证本文提出的退化机理模型，进行了一系列的电气分析和仿真分析。
{"title":"Comparative study on characteristics of GaN-based MIS-HEMTs with Al2O3 and Si3N4 gate insulators under Hot Carrier Degradation","authors":"Pei-Yu Wu, Xin-Ying Tsai, T. Chang, T. Tsai, S. Sze","doi":"10.1109/ICMTS55420.2023.10094072","DOIUrl":"https://doi.org/10.1109/ICMTS55420.2023.10094072","url":null,"abstract":"In GaN-based metal-insulatorsemiconductor high electron mobility transistors (GaNbased MIS HEMTs), Al2O3/Si3N4 bilayer-gate insulator- MIS HEMTs (Al2O3/Si3N4-MIS HEMTs) are considered to have the advantages of low gate leakage and low interface defects. This study will compare Si3N4 gate insulator-MIS HEMTs (Si3N4-MIS HEMTs) to discuss and clarify the abnormal deterioration mechanism of Al2O3/Si3N4-MIS HEMTs under Hot Carrier Effect (HCE). Therefore, in this study, the results of HCE between Si3N4-MIS HEMTs and Al2O3/Si3N4-MIS HEMTs are compared, and the abnormal HCS degradations in Al2O3/Si3N4-MIS HEMTs are discussed and explained in depth. A series of electrical and simulation analysis is conducted in order to verify the degradation mechanism model proposed in this study.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"365 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130959667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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