Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning

Abstract

Vertical integration of layers in a 3D IC exacerbates thermal problem especially for reliability degradation. Low reliability can not only damage the whole circuits but also cause unexpected performance loss. In this paper, we conduct the SA engine with rectangle-STSVs and double-STSVs for improving reliability. The earlier research indicates that the more STSVs a chip has, the better the reliability is. However, it also implies a larger area. Therefore, we develop a methodology to manipulate thermal-aware floorplan with the tradeoff among the number of STSVs, reliability, and area of a chip. Moreover, we manage our manipulated floorplan with precise thermal model for TTSVs insertion at via channel. Experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, thereby improving reliability. Furthermore, temperature can be maintained around 80°C with minimal TTSVs after inserting TTSVs.