{"title":"On parallel switch level fault simulation","authors":"C. A. Ryan, J. Tront","doi":"10.1109/VTEST.1993.313375","DOIUrl":null,"url":null,"abstract":"Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313375","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
