Savage16 - 16-bit RISC architecture general purpose microprocessor

Abstract

This paper describes the architecture and the internal structure of “Savage16”, a fully functional general purpose reduced instruction set microprocessor, with a modified Harvard, five stage pipeline architecture. The memory organization and key architecture elements are being described, as well as the hardware block diagram and the internal structure. A summary of the instruction set is presented, along with a brief description of the addressing modes.