Accurate Gate Charge Modeling of HV LDMOS Transistors for Power Circuit Applications

Abstract

Accurate modeling of the gate-drain capacitance Cgd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved Cgd model, based on the physics that the drift region under the poly-gate is fully depleted at high Vdg, and validate our model against gate charge measurements for both n-and p-type 90V LDMOS transistors.