Characterization of reverse-bias leakage currents and their effect on the holding time characteristics of MOS dynamic RAM circuits

Abstract

An experimental study has been performed with respect to the characterization of dynamic charge storage in MOS RAM circuits. Results of this investigation indicate that the deleterious effects of metallically decorated crystal defects can be successfully minimized by the design of proper impurity gettering cycles. Furthermore, it has been shown that the resulting p-n junction and MOS reverse-bias leakage currents of optimally processed structures are solely dominated at elevated temperature (T≥40°C) by the inherent diffusion currents (Ea≈1.1 eV). This type of leakage current is not only a function of the Si substrate parameters, but is also area and geometry dependent; and the implications of this upon RAM design, layout, and testing are discussed.