Efficient Resource Shared RISC-V Multicore Processor

Abstract

Edge computing pushes the computational loads from the cloud to embedded devices, where data would be processed near the data source. Heterogeneous multicore architecture is believed to be a promising solution to fulfill the edge computational requirement. In FPGAs, the heterogeneous multicore is realized as multiple soft processor cores with custom processing elements. Since FPGA is a resource-constrained device, sharing the hardware resources among the soft processor cores can be advantageous. Some research has focused on the sharing resources among soft processors, but they do not study how much FPGA logic is minimized for a five-stage pipeline processor. This paper proposes the microarchitecture of a five-stage pipeline scalar processor that enables the sharing of functional units for execution among the multiple cores. We then investigate the performance and hardware resource utilization for a four-core processor. We find that sharing different functional units can save the LUT usage to 23.5% and DSP usage to 75%. We analyze the performance impact of sharing from the Embench benchmark program by simulating the same program in all four cores. Our simulation results indicate that based on the sharing configuration, the average performance drops from 2.9% to 22.3%.