N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama
{"title":"Cluster-preforming-deposited amorphous WSin (n = 12) insertion film of low SBH and high diffusion barrier for direct Cu contact","authors":"N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama","doi":"10.1109/IEDM.2017.8268442","DOIUrl":null,"url":null,"abstract":"The insertion of an amorphous WSin (n = 12) film composed of W-atom-encapsulated Sin cage clusters is demonstrated to reduce the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly extending the estimated TDDB lifetime to > 10 years at 100 °C under 5 MV/cm stress for Cu MOS capacitors. This film was formed with an excellent contact hole coverage by using WF6 and SiH4 gas sources in a hot-wall thermal reactor. These film properties enable the direct Cu contact at S/D in CMOS.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268442","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The insertion of an amorphous WSin (n = 12) film composed of W-atom-encapsulated Sin cage clusters is demonstrated to reduce the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly extending the estimated TDDB lifetime to > 10 years at 100 °C under 5 MV/cm stress for Cu MOS capacitors. This film was formed with an excellent contact hole coverage by using WF6 and SiH4 gas sources in a hot-wall thermal reactor. These film properties enable the direct Cu contact at S/D in CMOS.