{"title":"Digital assisted high-order multi-bit analog to digital ramp converters","authors":"Yao Liu, E. Bonizzoni, F. Maloberti","doi":"10.1109/ECCTD.2011.6043598","DOIUrl":null,"url":null,"abstract":"The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are presented and discussed.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2011.6043598","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are presented and discussed.
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