Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043298
M. Lutovac, J. Ćertić, L. Milic
A new filter class with variable cut-off frequency is designed based on elliptic filter sharpening technique. A higher order IIR filter with a sharp transition band is constructed by using several identical low-order EMQF (elliptic minimal Q-factors) filters and an additional compensating section. The stopband attenuation is achieved by cascading EMQF subfilters, and the compensation section is designed to minimize the overall passband ripple. For the tuning of the cut-off frequency we propose a simple version of the spectral parameter approximation technique. Low-degree approximating polynomials are developed to represent coefficients of the EMQF subfilters and coefficients of the compensating section in terms of the passband cut-off frequency. In the tuning procedure, the new coefficient values are obtained by the polynomial evaluation consisting of several multiplications and additions. The analytical methods are derived for the filter design and for the tuning procedure. Design and implementation of sharp variable filters is illustrated by means of examples.
{"title":"A class of digital filters with variable cut-off based on EMQF filter sections and sharpening method","authors":"M. Lutovac, J. Ćertić, L. Milic","doi":"10.1109/ECCTD.2011.6043298","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043298","url":null,"abstract":"A new filter class with variable cut-off frequency is designed based on elliptic filter sharpening technique. A higher order IIR filter with a sharp transition band is constructed by using several identical low-order EMQF (elliptic minimal Q-factors) filters and an additional compensating section. The stopband attenuation is achieved by cascading EMQF subfilters, and the compensation section is designed to minimize the overall passband ripple. For the tuning of the cut-off frequency we propose a simple version of the spectral parameter approximation technique. Low-degree approximating polynomials are developed to represent coefficients of the EMQF subfilters and coefficients of the compensating section in terms of the passband cut-off frequency. In the tuning procedure, the new coefficient values are obtained by the polynomial evaluation consisting of several multiplications and additions. The analytical methods are derived for the filter design and for the tuning procedure. Design and implementation of sharp variable filters is illustrated by means of examples.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115421711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043389
T. Zsedrovits, Á. Zarándy, B. Vanek, T. Péni, J. Bokor, T. Roska
One of the missing critical on-board safety equipment of the Unmanned Arial Vehicles (UAVs) is the collision avoidance system. In 2010 we launched a project to research and develop an SAA system for UAS. As the system will be on-board in a small aircraft we have to minimize the weight, the volume, and the power consumption. The acceptable power consumption is 1–2W and the mass of the control system is maximum 300–500g. Here we present the concept of a visual input based See and Avoid (SAA) system. This paper introduces the long range visual detection algorithm and the implementation aspect of the many core processor device.
无人驾驶飞行器(uav)缺少的关键机载安全设备之一是避碰系统。2010年，我们启动了一个项目，研究和开发用于无人机的SAA系统。由于该系统将安装在小型飞机上，我们必须将重量、体积和功耗降至最低。可接受的功耗为1-2W，控制系统的最大质量为300-500g。在这里，我们提出了一个基于视觉输入的See and Avoid (SAA)系统的概念。本文介绍了远程视觉检测算法及其多核处理器器件的实现方面。
{"title":"Visual Detection and Implementation Aspects of a UAV See and Avoid System","authors":"T. Zsedrovits, Á. Zarándy, B. Vanek, T. Péni, J. Bokor, T. Roska","doi":"10.1109/ECCTD.2011.6043389","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043389","url":null,"abstract":"One of the missing critical on-board safety equipment of the Unmanned Arial Vehicles (UAVs) is the collision avoidance system. In 2010 we launched a project to research and develop an SAA system for UAS. As the system will be on-board in a small aircraft we have to minimize the weight, the volume, and the power consumption. The acceptable power consumption is 1–2W and the mass of the control system is maximum 300–500g. Here we present the concept of a visual input based See and Avoid (SAA) system. This paper introduces the long range visual detection algorithm and the implementation aspect of the many core processor device.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117247265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043852
J. Hospodka, P. Sovka, B. Psenicka
The aim of this paper is to describe a method of filter bank realization using the switched capacitor (SC) technique. The analysis of steps needed for this realization is performed. The correct solution requires the IIR filter bank synthesis followed by the conversion to SC circuits. Due to simplicity only the two-channel filter bank is used. The main points of the whole design procedure and key recommendations for the realization are given. The complete design of SC circuits was performed by PraCAn package in Maple program and resulted circuit structures were simulated in WinSpice. The obtained results are in agreement with theoretical derivations
{"title":"Design and realization of a filter bank by switched capacitor technique","authors":"J. Hospodka, P. Sovka, B. Psenicka","doi":"10.1109/ECCTD.2011.6043852","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043852","url":null,"abstract":"The aim of this paper is to describe a method of filter bank realization using the switched capacitor (SC) technique. The analysis of steps needed for this realization is performed. The correct solution requires the IIR filter bank synthesis followed by the conversion to SC circuits. Due to simplicity only the two-channel filter bank is used. The main points of the whole design procedure and key recommendations for the realization are given. The complete design of SC circuits was performed by PraCAn package in Maple program and resulted circuit structures were simulated in WinSpice. The obtained results are in agreement with theoretical derivations","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126024776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043846
F. Centurelli, P. Monsurrò, G. Scotti, A. Trifiletti
In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter, that can give rise to some clock feedthrough in continuous-time applications. However good linearity with limited clock intermodulation can be achieved by careful design. An opamp in 65-nm CMOS technology featuring the proposed input stage is operational for supply voltages as low as 0.5 V, with a net linearity improvement with respect to a simple pseudo-differential stage.
{"title":"A very low-voltage differential amplifier for opamp design","authors":"F. Centurelli, P. Monsurrò, G. Scotti, A. Trifiletti","doi":"10.1109/ECCTD.2011.6043846","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043846","url":null,"abstract":"In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter, that can give rise to some clock feedthrough in continuous-time applications. However good linearity with limited clock intermodulation can be achieved by careful design. An opamp in 65-nm CMOS technology featuring the proposed input stage is operational for supply voltages as low as 0.5 V, with a net linearity improvement with respect to a simple pseudo-differential stage.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123754158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043652
G. Palumbo, M. Pennisi, R. Carvajal
Three representative class AB Current Mirror OTAs are analytically compared in term of the trade-off speed, current consumption and area. The approach presented allows to derive useful design guidelines. The analysis was validated by means of simulations considering a 90 nm CMOS technology.
{"title":"Figures of merit for class AB input stages","authors":"G. Palumbo, M. Pennisi, R. Carvajal","doi":"10.1109/ECCTD.2011.6043652","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043652","url":null,"abstract":"Three representative class AB Current Mirror OTAs are analytically compared in term of the trade-off speed, current consumption and area. The approach presented allows to derive useful design guidelines. The analysis was validated by means of simulations considering a 90 nm CMOS technology.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122884101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043851
F. Centurelli, P. Monsurrò, A. Trifiletti
In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10µA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has −50dB HD2 and −60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5VPP square wave is about 20ns.
{"title":"A class-AB flipped voltage follower output stage","authors":"F. Centurelli, P. Monsurrò, A. Trifiletti","doi":"10.1109/ECCTD.2011.6043851","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043851","url":null,"abstract":"In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10µA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has −50dB HD2 and −60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5VPP square wave is about 20ns.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043640
J. Aikio, T. Rahkonen
This paper describes how a novel distortion contribution analysis can be used efficiently for improving the linearity of a nonlinear circuit. The distortion analysis technique called Volterra-on-Harmonic-Balance calculates a distortion contributions in each tone and node for each nonlinear elements of the nonlinear devices in the circuit. As the analysis provides large amount of data, also the flow of interpreting the results contains many steps that are described in detail in this paper.
{"title":"Utilization of distortion contribution analysis","authors":"J. Aikio, T. Rahkonen","doi":"10.1109/ECCTD.2011.6043640","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043640","url":null,"abstract":"This paper describes how a novel distortion contribution analysis can be used efficiently for improving the linearity of a nonlinear circuit. The distortion analysis technique called Volterra-on-Harmonic-Balance calculates a distortion contributions in each tone and node for each nonlinear elements of the nonlinear devices in the circuit. As the analysis provides large amount of data, also the flow of interpreting the results contains many steps that are described in detail in this paper.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114189448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043644
C. Nemes, Z. Nagy, P. Szolgay
Computationally intensive problems can be represented with data-flow graphs and automatically transformed to locally controlled floating-point units via partitioning. In theory the lack of global control signals enables high performance implementation however placing and routing of the partitioned circuits are not trivial. In practice to create a high performance implementation the clusters should be placed efficiently on the surface of an FPGA using the physical constraining feature of CAD tools. In the paper a new partitioning strategy is presented which not only minimizes the number of cut nets but produce partition which can be mapped without long interconnections between the clusters. The new strategy is demonstrated during the automatic circuit generation from a complex mathematical expression. The proposed partitioning method produces more cut nets than common strategies however the resulting partition can be easily mapped and operate on significantly higher frequency.
{"title":"Efficient mapping of mathematical expressions to FPGAs: Exploring different design methodologies","authors":"C. Nemes, Z. Nagy, P. Szolgay","doi":"10.1109/ECCTD.2011.6043644","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043644","url":null,"abstract":"Computationally intensive problems can be represented with data-flow graphs and automatically transformed to locally controlled floating-point units via partitioning. In theory the lack of global control signals enables high performance implementation however placing and routing of the partitioned circuits are not trivial. In practice to create a high performance implementation the clusters should be placed efficiently on the surface of an FPGA using the physical constraining feature of CAD tools. In the paper a new partitioning strategy is presented which not only minimizes the number of cut nets but produce partition which can be mapped without long interconnections between the clusters. The new strategy is demonstrated during the automatic circuit generation from a complex mathematical expression. The proposed partitioning method produces more cut nets than common strategies however the resulting partition can be easily mapped and operate on significantly higher frequency.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043598
Yao Liu, E. Bonizzoni, F. Maloberti
The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are presented and discussed.
{"title":"Digital assisted high-order multi-bit analog to digital ramp converters","authors":"Yao Liu, E. Bonizzoni, F. Maloberti","doi":"10.1109/ECCTD.2011.6043598","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043598","url":null,"abstract":"The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12–14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are presented and discussed.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122143390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043303
T. Sánchez-Rodríguez, R. Carvajal, S. Pennisi, J. Galán
We present a low-voltage low-power CMOS tunable transconductor exploiting body gain boosting to increase the small-signal output resistance. As a distinctive feature, the proposed scheme allows the OTA transconductance to be tuned via the current biasing the gain-boosting circuit. The proposed transconductor has been designed in a 0.13-µm CMOS technology and powered from a 1.2-V supply. To show a possible application, a 0.5-MHz tunable third order Chebyshev low pass filter suitable for the Ultra Low Power Bluetooth Standard has been designed. The filter simulations show that all the requirements of the chosen standard are met, with good performance in terms of linearity, noise and power consumption.
{"title":"0.13-µm CMOS tunable transconductor based on the body-driven gain boosting technique with application in Gm-C filters","authors":"T. Sánchez-Rodríguez, R. Carvajal, S. Pennisi, J. Galán","doi":"10.1109/ECCTD.2011.6043303","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043303","url":null,"abstract":"We present a low-voltage low-power CMOS tunable transconductor exploiting body gain boosting to increase the small-signal output resistance. As a distinctive feature, the proposed scheme allows the OTA transconductance to be tuned via the current biasing the gain-boosting circuit. The proposed transconductor has been designed in a 0.13-µm CMOS technology and powered from a 1.2-V supply. To show a possible application, a 0.5-MHz tunable third order Chebyshev low pass filter suitable for the Ultra Low Power Bluetooth Standard has been designed. The filter simulations show that all the requirements of the chosen standard are met, with good performance in terms of linearity, noise and power consumption.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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