Integrated logic - Static induction transistor logic

Abstract

SOLID-STATE CIRCUITS are designed to minimize both delay time and operational power. The product of these is thought t o be constant, represented by a specific figure for each type of integrated circuit. The 12L structure has been shown to operate with the lowest switching energy’. The power efficiency of the Vertical Injection Logic (VIL) structure shows a further improvement, by a factor of two. However, its fabrication requires the use of 7-8 masks’. A new logic circuit structure is proposed Static Induction Transistor Logic (SITL) utilizing the static induction transistor ( SIT)3. This logic circuit permits a further reduction in the power-delay time product (theoretically 6 x and experimentally, one order of magnitude). In the case of 12L, it is made by a 3 or 4-mask technology. The packing density can be as high as 1000 gates/cm2. In this logic structure, the SITS are used as the output transistors and the lateral bipolar PNP transistor is used as the injector, as usual, as shown in Figure 1. The SIT consists of Nt drains on the top surface of the Nepitaxial layer, a Pt gate configured on both sides of the drain on the same surface and the space charge layer formed surrounding the drain regions, Nchannels penetrating the gate region below the drains and the N+ source substrate. The channels are about 2-3 p m in diamcter and are formed by lateral P-type diffusion. The fabrication process in this case is as follows. The Nepitaxial layer is grown on the N+ substrate, having a carrier concentration of 2-3 x 1013 cm-3 and a thickness of 4-5 pm. After oxidation and photolithography, B-diffused layers were formed as the gate regions of the SIT and the emitter of the injector (the lateral transistor), followed by the second oxidation. Then, the Nf -diffusion layers are formed as drain regions, followed by the opening of contact holes in the Si02 film, using the third photolithography. After A1 evaporation, the A1 film is selectively etched, and the ring oscillator formed, as shown in Figure 2.