Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis

Abstract

In this paper, we propose a layout-aware scan tree synthesis methodology. Scan tree can greatly reduce test data volume, which is very desirable in SOC testing. However, previous researches on scan tree synthesis have not considered routing issues in physical design, which may create a tree with excessively long routing path. In this paper we present a multi-layer multi-level scan tree synthesis method, in which both data compression and routing length are taken into account. Experimental results show that the proposed test method achieves high compression rate with limited routing overhead.