S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi
{"title":"Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes","authors":"S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi","doi":"10.1109/IEDM.2017.8268346","DOIUrl":null,"url":null,"abstract":"Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268346","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.
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