Influence of bit line twisting on the faulty behavior of DRAMs

Abstract

Bit line twisting is an effective design method commonly used to reduce the impact of bit line coupling noise in high density memory devices. This paper investigates the way bit line twisting influences the faulty behavior of DRAMs, based on an analytical evaluation of coupling effects on the one hand, and a simulation-based fault analysis using a Spice simulation model on the other. Two different DRAM twisting schemes, in addition to a third untwisted bit line scheme, are presented and analyzed. Both the analytical and the simulation-based evaluation results show that each scheme has its own specific impact on the faulty behavior. The same approach presented in the paper can be used to analyze the impact of other bit line twisting schemes on the memory faulty behavior.