A 22nm FD-SOI CMOS 2-way D-band Power Amplifier Achieving PAE of 7.7% at 9.6dBm OP1dB and 3.1% at 6dB Back-off by Leveraging Adaptive Back-Gate Bias Technique

Abstract

This work presents a 2-way 3-stage D-band Power Amplifier (PA) in 22nm FD-SOI technology. A dynamic 3-stage bias scaling technique is proposed for this PA. It is based on leveraging the back-gate terminal in CMOS FD-SOI technology to optimize the power consumption of each stage adaptive to the input power of the PA, and hence improve its overall PAE in the linear range, i.e. at OP1dB and power back-off. The PA has been fabricated on a die with the core area of 0.16mm 2. Small signal and large signal characteristics of the PA chip have been measured. At 1V supply voltage and frequency of 135GHz, it provides 14.2dB power gain with 20GHz and 52GHz 3-dB and 6-dB bandwidth, respectively. Measurement results show this PA achieves 7.7% and 3.1% PAE at 9.6 dBm OP1dB and 6dB back-off that features >1.5X and >2X improvement, respectively, compared to the state-of-the-art D-band PAs in CMOS technologies.