Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863165
M. Moosavifar, Yaswanth K. Cherivirala, D. Wentzloff
This paper presents a 900MHz ultra-low-power (ULP) receiver (RX) with -88dBm sensitivity and up to -58dB Signal-to-Interference Ratio (SIR) for the Internet of Things (IoT) applications. The receiver utilizes chirped On-Off-Keying (OOK) modulation for data reception. We proposed a mixer-first receiver leveraging a chirped Miller N-path filter, to achieve low-power operation while ensuring strong in-band and out-of-band interference rejection as well as sufficient RX sensitivity. A novel 4-phase chirped Miller N-path filter, using a high quality factor time-varying narrowband frequency response, is introduced in this work to facilitate bandpass filtering of the wideband chirp-OOK modulated signal, that results in enhanced RX interference tolerance. The RX chip is designed and fabricated in a CMOS 65nm technology and consumes 320μW at 5kb/s data-rate, while achieving -88dBm sensitivity at 10–3 Bit-Error-Rate (BER).
{"title":"A 320μW Receiver with -58dB SIR Leveraging a Time-Varying N-Path Filter","authors":"M. Moosavifar, Yaswanth K. Cherivirala, D. Wentzloff","doi":"10.1109/RFIC54546.2022.9863165","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863165","url":null,"abstract":"This paper presents a 900MHz ultra-low-power (ULP) receiver (RX) with -88dBm sensitivity and up to -58dB Signal-to-Interference Ratio (SIR) for the Internet of Things (IoT) applications. The receiver utilizes chirped On-Off-Keying (OOK) modulation for data reception. We proposed a mixer-first receiver leveraging a chirped Miller N-path filter, to achieve low-power operation while ensuring strong in-band and out-of-band interference rejection as well as sufficient RX sensitivity. A novel 4-phase chirped Miller N-path filter, using a high quality factor time-varying narrowband frequency response, is introduced in this work to facilitate bandpass filtering of the wideband chirp-OOK modulated signal, that results in enhanced RX interference tolerance. The RX chip is designed and fabricated in a CMOS 65nm technology and consumes 320μW at 5kb/s data-rate, while achieving -88dBm sensitivity at 10–3 Bit-Error-Rate (BER).","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114422122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863091
Venkata S. Rayudu, Ki Yong Kim, D. Pan, R. Gharpurey
A downconversion receiver employing a switch-based N-path filter with reduced input harmonic response and harmonic translation from around the $3^{text{rd}}$ and the $5^{text{th}}$ LO harmonics is presented. The N-path filter employs 8 paths, and is embedded inside a harmonic-selective negative feedback loop. A pulse-width-modulated LO (PWM-LO) is used in the feedback upconverter to reduce the noise injected around the LO fundamental at the input of the N-path downconverter. The architecture is verified in a 65-nm CMOS technology. Approximately 15–18 dB reduction in the $3mathrm{f}_{LO}$ and $5mathrm{f}_{LO}$ harmonic response, and 8–10 dB enhancement in harmonic-blocker 3-dB compression is observed in measurement. The use of a PWM-LO, instead of a rectangular clock in the upconverter, improves noise figure by nearly 4 dB.
{"title":"A Feedback-Based N-Path Receiver with Reduced Input-Node Harmonic Response","authors":"Venkata S. Rayudu, Ki Yong Kim, D. Pan, R. Gharpurey","doi":"10.1109/RFIC54546.2022.9863091","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863091","url":null,"abstract":"A downconversion receiver employing a switch-based N-path filter with reduced input harmonic response and harmonic translation from around the $3^{text{rd}}$ and the $5^{text{th}}$ LO harmonics is presented. The N-path filter employs 8 paths, and is embedded inside a harmonic-selective negative feedback loop. A pulse-width-modulated LO (PWM-LO) is used in the feedback upconverter to reduce the noise injected around the LO fundamental at the input of the N-path downconverter. The architecture is verified in a 65-nm CMOS technology. Approximately 15–18 dB reduction in the $3mathrm{f}_{LO}$ and $5mathrm{f}_{LO}$ harmonic response, and 8–10 dB enhancement in harmonic-blocker 3-dB compression is observed in measurement. The use of a PWM-LO, instead of a rectangular clock in the upconverter, improves noise figure by nearly 4 dB.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121200109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863183
Jie Zhou, H. Qian, Bingzheng Yang, Xun Luo
In this paper, a 4-element digital-modulated phased-array transmitter (TX) based on quadrature switched/ floated-capacitor power amplifiers (SFCPAs) and reconfigurable switched-capacitor tuning lines (RSCTLs) is proposed. Phase shifting in each element is achieved by hybrid coarse and fine phase-tuning techniques. The SFCPAs with quadrature rotation is presented for coarse phase tuning, while the RSCTLs is used for fine phase tuning. To improve the efficiency at deep power back-off (PBO) peaks, a 4-to-1 reconfigurable transformer is introduced in the SFCPAs. Meanwhile, a 1-by-4 active power divider is utilized for isolation improvement among each elements. The proposed phased-array TX is implemented in conventional 40-nm CMOS technology. The fabricated phased-array TX features 28.4dBm peak output power and 37.9% peak system efficiency. In addition, it supports 0/3/6/9/12/15-dB PBOs efficiency enhancement and 15-bit phase-tuning resolution.
本文提出了一种基于正交开关/浮动电容功率放大器(SFCPAs)和可重构开关电容调谐线(rsctl)的4元数字调制相控阵发射机(TX)。每个元件的相移是通过粗调和精调相混合技术实现的。提出了带正交旋转的sfcpa用于粗相位调谐，而rsctl用于精细相位调谐。为了提高深功率回退(PBO)峰值时的效率，在sfcpa中引入了4对1可重构变压器。同时，采用1 × 4有源功率分压器提高各元件之间的隔离度。所提出的相控阵TX采用传统的40纳米CMOS技术实现。所制相控阵TX的峰值输出功率为28.4dBm，峰值系统效率为37.9%。此外，它还支持0/3/6/9/12/15 db PBOs效率增强和15位相位调谐分辨率。
{"title":"A Quadrature-Rotation Phased-Array Transmitter with 15-Bit Phase Tuning and 0/3/6/9/12/15-dB PBOs Efficiency Enhancement","authors":"Jie Zhou, H. Qian, Bingzheng Yang, Xun Luo","doi":"10.1109/RFIC54546.2022.9863183","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863183","url":null,"abstract":"In this paper, a 4-element digital-modulated phased-array transmitter (TX) based on quadrature switched/ floated-capacitor power amplifiers (SFCPAs) and reconfigurable switched-capacitor tuning lines (RSCTLs) is proposed. Phase shifting in each element is achieved by hybrid coarse and fine phase-tuning techniques. The SFCPAs with quadrature rotation is presented for coarse phase tuning, while the RSCTLs is used for fine phase tuning. To improve the efficiency at deep power back-off (PBO) peaks, a 4-to-1 reconfigurable transformer is introduced in the SFCPAs. Meanwhile, a 1-by-4 active power divider is utilized for isolation improvement among each elements. The proposed phased-array TX is implemented in conventional 40-nm CMOS technology. The fabricated phased-array TX features 28.4dBm peak output power and 37.9% peak system efficiency. In addition, it supports 0/3/6/9/12/15-dB PBOs efficiency enhancement and 15-bit phase-tuning resolution.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114734168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863095
Jun-Chau Chien
This paper presents a single-element VNA electronic calibration (E-Cal) technique implemented in CMOS technology. The structure employs a transmission line (t-line) loaded with twenty distributed switches whose impedance states can be independently modulated during S-parameter measurements. An algorithm that leverages the implementation concepts from the one-port offset-shorts and the two-port Line-Reflect-Reflect-Match $(LRRM)$ calibrations and takes advantage of the loading periodicity and the structure layout symmetry is developed. The calibration method is justified using a 65-nm CMOS test chip and the measurement results are compared with on-chip one-tier TRL calibration using both passive and active devices up to 67 GHz.
{"title":"Millimeter-wave VNA Calibration using a CMOS Transmission Line with Distributed Switches","authors":"Jun-Chau Chien","doi":"10.1109/RFIC54546.2022.9863095","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863095","url":null,"abstract":"This paper presents a single-element VNA electronic calibration (E-Cal) technique implemented in CMOS technology. The structure employs a transmission line (t-line) loaded with twenty distributed switches whose impedance states can be independently modulated during S-parameter measurements. An algorithm that leverages the implementation concepts from the one-port offset-shorts and the two-port Line-Reflect-Reflect-Match $(LRRM)$ calibrations and takes advantage of the loading periodicity and the structure layout symmetry is developed. The calibration method is justified using a 65-nm CMOS test chip and the measurement results are compared with on-chip one-tier TRL calibration using both passive and active devices up to 67 GHz.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863092
Bichoy Bahr, D. Griffith, Ali Kiaei, Thomas Tsai, Ryan Smith, B. Haroun
This paper presents a low-power, low-phase noise class-C Bulk Acoustic Wave (BAW) oscillator. It achieves a FOM of −206.5 dB at 1 kHz offset, enabling low-power, crystal-less SoC implementation for multiple wireless standards. A reference oscillator module for SoC integration is presented with a corresponding optimal tuning procedure for best phase noise performance. Power efficient class-C operation, reduced device count, and amplitude trimming, allow for 3 dB $FOM$ and $FOM_{Q}$ improvement over state-of-the-art GHz MEMS-based oscillators.
提出了一种低功耗、低相位噪声的c类体声波振荡器。它在1 kHz偏置下实现- 206.5 dB的FOM，可实现多种无线标准的低功耗，无晶体SoC实现。提出了一种SoC集成参考振荡器模块，并给出了相应的最佳相位噪声调谐程序。功率高效的c类操作，减少器件数量和幅度微调，使其比最先进的GHz mems振荡器提高3 dB $FOM$和$FOM_{Q}$。
{"title":"Class-C BAW Oscillator Achieving a Close-in FOM of 206.5dB at 1kHz with Optimal Tuning for Narrowband Wireless Systems","authors":"Bichoy Bahr, D. Griffith, Ali Kiaei, Thomas Tsai, Ryan Smith, B. Haroun","doi":"10.1109/RFIC54546.2022.9863092","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863092","url":null,"abstract":"This paper presents a low-power, low-phase noise class-C Bulk Acoustic Wave (BAW) oscillator. It achieves a FOM of −206.5 dB at 1 kHz offset, enabling low-power, crystal-less SoC implementation for multiple wireless standards. A reference oscillator module for SoC integration is presented with a corresponding optimal tuning procedure for best phase noise performance. Power efficient class-C operation, reduced device count, and amplitude trimming, allow for 3 dB $FOM$ and $FOM_{Q}$ improvement over state-of-the-art GHz MEMS-based oscillators.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125728599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863082
F. Gianesello, A. Fleury, F. Julien, J. Durá, S. Monfray, S. Dhar, C. Legrand, J. Amouroux, B. Gros, L. Welter, C. Charbuillet, P. Cathelin, E. Canderle, N. Vulliet, E. Escolier, L. Antunes, E. Granger, P. Fornara, C. Rivero, G. Bertrand, P. Chevalier, A. Régnier, D. Gloria
RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{text{ON}}times C_{text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.
{"title":"Advanced 200-mm RF SOI Technology exhibiting $78 text{fs} mathrm{R}_{text{ON}}times mathrm{C}_{text{OFF}}$ and 3.7 V breakdown voltage targeting sub 6 GHz 5G FEM","authors":"F. Gianesello, A. Fleury, F. Julien, J. Durá, S. Monfray, S. Dhar, C. Legrand, J. Amouroux, B. Gros, L. Welter, C. Charbuillet, P. Cathelin, E. Canderle, N. Vulliet, E. Escolier, L. Antunes, E. Granger, P. Fornara, C. Rivero, G. Bertrand, P. Chevalier, A. Régnier, D. Gloria","doi":"10.1109/RFIC54546.2022.9863082","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863082","url":null,"abstract":"RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{text{ON}}times C_{text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129122462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863077
Zhanghao Yu, Wei Wang, Joshua C. Chen, Zhiyu Chen, Yan He, Amanda Singer, Jacob T. Robinson, Kaiyuan Yang
This paper presents a hardware platform for wireless mm-sized bio-implant networks, exploiting adaptive magnetoelectric power transfer and novel schemes for efficient bidirectional multi-access communication. The closed-loop power control mitigates power delivery fluctuations caused by distance and alignment change and avoids redundant power of the external transceiver. The system also enables simultaneous power and time-domain modulated downlink data with a 5% peak power transfer efficiency and a 62.3-kbps maximum data rate at 340-kHz carrier frequency; multi-access uplink of all the implants enabled by individually programmed IF with a 40-kbps maximum data rate at 31-MHz carrier frequency; and more than 6-cm distance between the implant and the external TRX.
{"title":"A Wireless Network of 8.8-mm3 Bio-Implants Featuring Adaptive Magnetoelectric Power and Multi-Access Bidirectional Telemetry","authors":"Zhanghao Yu, Wei Wang, Joshua C. Chen, Zhiyu Chen, Yan He, Amanda Singer, Jacob T. Robinson, Kaiyuan Yang","doi":"10.1109/RFIC54546.2022.9863077","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863077","url":null,"abstract":"This paper presents a hardware platform for wireless mm-sized bio-implant networks, exploiting adaptive magnetoelectric power transfer and novel schemes for efficient bidirectional multi-access communication. The closed-loop power control mitigates power delivery fluctuations caused by distance and alignment change and avoids redundant power of the external transceiver. The system also enables simultaneous power and time-domain modulated downlink data with a 5% peak power transfer efficiency and a 62.3-kbps maximum data rate at 340-kHz carrier frequency; multi-access uplink of all the implants enabled by individually programmed IF with a 40-kbps maximum data rate at 31-MHz carrier frequency; and more than 6-cm distance between the implant and the external TRX.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863153
Erez Zolkov, Nimrod Ginzberg, E. Cohen
In this work, we propose a fully integrated transceiver for frequency-division and half duplex wireless operation based on a quadrature balanced N-path mixer-first architecture. The quadrature balanced N-path transceiver (QBNT) comprises a quadrature hybrid and two identical mixer-first receivers (MFRXs), presenting a short circuit and 50 ohms matching in the transceiver (TX) and receiver (RX) bands, respectively. The TX power reflects at the MFRXs' interface and adds up in-phase at the antenna, while the RX signal from the antenna is reconstructed in phase in digital baseband, with the TX noise cancelled at RX regardless of antenna voltage standing wave ratio. QBNT equations and design considerations are shown. An integrated QBNT prototype was fabricated in TSMC 65nm CMOS process as a proof of concept, occupying an active area of 2.96 mm2, The QBNT operates at the frequency range between 0.75-2 GHz with a TX-RX offset above 200 MHz. It achieves RX noise figure (NF) of 2.8-5.8 dB, RXB1dB of 18 dBm, TX-ANT OIP3 of 27.3 dBm and 29.5 dBm in FDD and half duplex (HD) modes, respectively. The RX and TX (at OP1dB) consume DC power of 82–130 m Wand 254 m W, respectively.
{"title":"An Integrated Reconfigurable SAW-Less Quadrature Balanced N-Path Transceiver for Frequency-Division and Half Duplex Wireless","authors":"Erez Zolkov, Nimrod Ginzberg, E. Cohen","doi":"10.1109/RFIC54546.2022.9863153","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863153","url":null,"abstract":"In this work, we propose a fully integrated transceiver for frequency-division and half duplex wireless operation based on a quadrature balanced N-path mixer-first architecture. The quadrature balanced N-path transceiver (QBNT) comprises a quadrature hybrid and two identical mixer-first receivers (MFRXs), presenting a short circuit and 50 ohms matching in the transceiver (TX) and receiver (RX) bands, respectively. The TX power reflects at the MFRXs' interface and adds up in-phase at the antenna, while the RX signal from the antenna is reconstructed in phase in digital baseband, with the TX noise cancelled at RX regardless of antenna voltage standing wave ratio. QBNT equations and design considerations are shown. An integrated QBNT prototype was fabricated in TSMC 65nm CMOS process as a proof of concept, occupying an active area of 2.96 mm2, The QBNT operates at the frequency range between 0.75-2 GHz with a TX-RX offset above 200 MHz. It achieves RX noise figure (NF) of 2.8-5.8 dB, RXB1dB of 18 dBm, TX-ANT OIP3 of 27.3 dBm and 29.5 dBm in FDD and half duplex (HD) modes, respectively. The RX and TX (at OP1dB) consume DC power of 82–130 m Wand 254 m W, respectively.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122969509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863152
Lantao Wang, Jonas Meier, Johannes Bastl, Tim Lauber, Andreas Köllmann, Ulrich Möhlmann, Michael Hanhart, Alexander Meyer, C. Nardi, R. Wunderlich, S. Heinen
This paper presents an 8.2-10.2 GHz digitally controlled oscillator (DCO) in a 28 nm technology. The proposed DCO utilizes a switchable capacitor (SC) structure with a constantly conducting NMOS pair, featuring an SC bank with unitary cells arranged in a matrix. With the unitary weighted capacitor bank, the DCO demonstrates an inherently monotonic tuning with a range of 24.3 %. The finest tuning resolution is 17 kHz thanks to the customized fringe capacitor. The DCO shows a phase noise of −115.1 dBc/Hz at 1 MHz offset from 9 GHz carrier frequency with 13 m W power consumption, achieving a −183 dBc/Hz FoM and −190.6 dBc/Hz $mathbf{FoM}_{mathrm{T}}$.
{"title":"An 8.2-10.2 GHz Digitally Controlled Oscillator in 28-nm CMOS Using Constantly-Conducting NMOS Biased Switchable Capacitor","authors":"Lantao Wang, Jonas Meier, Johannes Bastl, Tim Lauber, Andreas Köllmann, Ulrich Möhlmann, Michael Hanhart, Alexander Meyer, C. Nardi, R. Wunderlich, S. Heinen","doi":"10.1109/RFIC54546.2022.9863152","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863152","url":null,"abstract":"This paper presents an 8.2-10.2 GHz digitally controlled oscillator (DCO) in a 28 nm technology. The proposed DCO utilizes a switchable capacitor (SC) structure with a constantly conducting NMOS pair, featuring an SC bank with unitary cells arranged in a matrix. With the unitary weighted capacitor bank, the DCO demonstrates an inherently monotonic tuning with a range of 24.3 %. The finest tuning resolution is 17 kHz thanks to the customized fringe capacitor. The DCO shows a phase noise of −115.1 dBc/Hz at 1 MHz offset from 9 GHz carrier frequency with 13 m W power consumption, achieving a −183 dBc/Hz FoM and −190.6 dBc/Hz $mathbf{FoM}_{mathrm{T}}$.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-19DOI: 10.1109/RFIC54546.2022.9863112
Armagan Dascurcu, Sohail Ahasan, Ali Binaie, Kuei Jih Lu, A. Natarajan, H. Krishnaswamy
Channel aggregation at mm-wave enables extremely high data rates, but necessitates high-speed data converters. This paper presents an alternative approach leveraging HRM-based frequency interleaving (FI), which relaxes the requirements on the data converters, reducing their power consumption and cost. The implemented 45nm RF SOI chipset includes 4-element 60GHz phased-array RX and TX chips, and 4-channel TX and RX baseband (BB) FI channelizer chips, which channelize 8GHz of bandwidth (BW) over 59–67 G Hz into 4 channels. Measured link results indicate that the BB FI channelizers and 60GHz phased array ICs together achieve sufficient SNDR in each channel to support 16-QAM and 64-QAM modulations over wide bandwidths, enabling wireless links at 32Gbps and beyond.
{"title":"A 60GHz Phased Array Transceiver Chipset in 45nm RF SOI Featuring Channel Aggregation Using HRM-Based Frequency Interleaving","authors":"Armagan Dascurcu, Sohail Ahasan, Ali Binaie, Kuei Jih Lu, A. Natarajan, H. Krishnaswamy","doi":"10.1109/RFIC54546.2022.9863112","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863112","url":null,"abstract":"Channel aggregation at mm-wave enables extremely high data rates, but necessitates high-speed data converters. This paper presents an alternative approach leveraging HRM-based frequency interleaving (FI), which relaxes the requirements on the data converters, reducing their power consumption and cost. The implemented 45nm RF SOI chipset includes 4-element 60GHz phased-array RX and TX chips, and 4-channel TX and RX baseband (BB) FI channelizer chips, which channelize 8GHz of bandwidth (BW) over 59–67 G Hz into 4 channels. Measured link results indicate that the BB FI channelizers and 60GHz phased array ICs together achieve sufficient SNDR in each channel to support 16-QAM and 64-QAM modulations over wide bandwidths, enabling wireless links at 32Gbps and beyond.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"50 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114130975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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