Interval Based X-Masking for Scan Compression Architectures

Abstract

Test stimulus and response compaction (scan compression) in scan is increasingly becoming an integral part of today's design-for-test (DFT) methodology for achieving high quality test at lower costs. Current generation integrated circuit's (ICs) are very complex designs that produce a large number of unknown values (Xs) during response capture in scan testing. Response compaction techniques have been shown to be very effective in dealing with any distribution of the Xs while not compromising on the test coverage. However, as the number of scan in pins reduce, the X-tolerance capability of these techniques degrades rapidly. In this paper we discuss interval based response compaction scheme for scan compression architectures. We present an analysis to show that very high X-tolerance can be achieved with a small number of scan-in pins and with no loss of test coverage. We also show that this eventually translates into higher compression ratio and lower test data volume.