An algorithm for Via minimization in two layer channel routing of VLSI design

Abstract

Via minimization plays an increasingly important role in the routing phase in the design process of VLSI circuits and systems. A via is an electrical connection that establishes the connectivity between two layers. Vias are established at points where a net changes layer. But if the number of vias is more, then it not only reduces the reliability of the product but also causes delay and affects the circuit performance. Therefore, via minimization plays an increasingly vital role in the efficient yield of the circuit. In this paper, we devise an algorithm for reducing the number of vias by using the concepts of maximum independent set, net intersection graph and segment intersection graph. Also in this approach the number of horizontal tracks is minimized, thus minimizing the routing area.