A new extraction method of retention time from the leakage current in 0.23 /spl mu/m DRAM memory cell

Abstract

The retention time distributions of DRAM memory cell with 0.23 /spl mu/m design rule and STI (Shallow Trench Isolation) have been investigated for several process splits that are designed to increase the retention time. A new extraction method of retention time in memory cell is proposed from the cell leakage current behavior at the general test pattern of memory cell array structure. The 50% bit failure time of memory cell is calculated by the proposed method and compared with the measured retention time. The calculated retention time is very well matched with the measured result in several process conditions of memory cell. Thus, this method can be used for extraction of the retention time of high-density DRAM memory (below 0.23 /spl mu/m) from the cell leakage current.