Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs

Abstract

In this paper, we propose delay-compensation techniques for subthreshold digital circuits. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. To mitigate such variations, threshold-voltage monitoring and supply-voltage scaling techniques are adopted. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from log-normal to normal. The coefficient of variation for the proposed technique is 31%.