A high performance 4K static RAM fabricated with an advanced MOS technology

Abstract

combining MOS device scaling’ with on chip substrate bias generation’. By reducing the physical parameters of the MOS device by a fixed scaling factor, circuit density and performance were increased while decreasing active circuit power. The advanced technology uses polysilicon ate lengths under 4 p and a gate oxide thickness less than 1000 R . Shallow junctions ( < l p ) are obtained by using arsenic as the source-drain diffusant. In addition, oxide isolation and depletion load processing are employed to improve further circuit performance and density. Substrate bias is used to reduce device body effect The high performance of the MOS memory was achieved by circuit is a simple differential amplifier with dc feedback to provide for process and temperature compensation. The powerdown mode is controlled by chip enable. During powerdown (CE high), the memory array is completely deselected and the column and I/O buss is reset to a threshold below supply voltage. By balancing the internal circuitry during powerdown, it is possible to overcome the additional chip enable powerup delay and obtain a powerup access time equal to the address access time; Figure 3. Typically, the RAM accesses in 45ns and has an active power dissipation of 500mW. Powerup does not display current spikes typical of dynamic circuitry and powerdown takes less than 3011s. A summary of the device characteristics is presented in Table 1.