{"title":"Spice modelling flow for ESD simulation of CMOS ICs","authors":"G. Langguth, A. Ille","doi":"10.1109/EOSESD.2016.7592553","DOIUrl":null,"url":null,"abstract":"A SPICE based simulation flow is proposed for ESD verification in standard analog simulation environment. Models contain ESD specific sub-circuits and failure thresholds which are activated on demand. Good agreement with experimental data is proven including bipolar operation and the triggering of parasitic paths. The flow has been successfully tested on real designs.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2016.7592553","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A SPICE based simulation flow is proposed for ESD verification in standard analog simulation environment. Models contain ESD specific sub-circuits and failure thresholds which are activated on demand. Good agreement with experimental data is proven including bipolar operation and the triggering of parasitic paths. The flow has been successfully tested on real designs.
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