A VLSI link-level controller

Abstract

THIS PAPER WILL DISCUSS an IC that performs complete link-level control according to a communication protocol that is a superset of the CCITT X.25 level 2 LAPB protocol because it includes the exchange identification frames. In addition to the standard modulo 8 frame sequencing and 16b CRC error detection method set forth by the protocol, the circuit affords a programmable window size (K) comparator, programmable information field length (Nl) and retransmission (N2) counters, and four programmable link assurance timers (T1 through T4). The IC automatically maintains the link by handling supervisory and unnumbered frames without user intervention, interrupting the host CPU only when it requires attention. Typical interrupts are transmitted block acknowledged and packet received: these inform the host that data in the buffers (defined during set up) has been sent or received and require user attention. Other interrupts inform the user of the physical link status. The interface between the IC and the physical link layer (level 1 ) consists of seven signals: request-to-send, clear-to-send, transmit data, received data, transmit clock, receive clock, and receiver carrier detect. These signals assume the usual RS-232 definitions. Finally, a DMA is used to support the circuit to host interface. The host defines regions of memory for the IC wherein i t sets up transmit data buffers, receive data buffers, and buffer management tables. The host is able to monitor the management tables to aid in the transfer of data to and from the data buffers. The circuit consists of a transmitter, receiver, main controller, and interface unit as shown in Figure 1. These four components are essentially independent and loosely coupled. The transmitter and receiver handle low-level aspects of the protocol such as flag generation and detection, zero-bit insertion and deletion, and CRC generation and checking. In addition, the receiver is required to identify and classify all incoming frames so that the main controller can queue and transmit the appropriate responses. A three-channel DMA and interrupt circuit form the heart of the user interface. Both the transmitter and receiver have their own DMA channel to transfer data to and from local memory. The third channel automatically maintains the buffer management tables. With the interrupt handler, it is possible to prioritize and inhibit interrupt collisions generated by the various sections of the chip. 1