WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm

Abstract

This paper describes the design flow of the standard cell characterization on five different technologies and integration of its results with other VLSI tools processes that can be duplicated and implemented for the research and education in the academia. In this proposed work, one design flow is on non-fabricable technology of open-source false-technology FreePDK45 of 45 nm CMOS technology [1]. The other design flows are in the fabricable technology in 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. The design flow are automated to simplify the students with intricacy of the tools. This design flows in this work are automated for the tool, Virtuoso Liberate from Cadence Design Systems and students can easily adopt it as part of the VLSI design class curriculum. This characterization flow precisely models the electrical characteristics of the cell that has been subjected to different input variables as explained below. The characterized models are of high demand in other design tools used in between RTL to GDSII process flow.