On code coverage measurement for Verilog-A

Abstract

In order to verify the integration of digital circuits and analog circuits in a SOC design, HDL-A languages are proposed to describe analog circuits such that they can be simulated together with the digital circuits described in HDL code. For digital circuits, coverage-driven approach has been widely used to verify the quality of HDL designs. However, for analog models, there are still no suitable solutions to gauge their quality. Therefore, in this paper, we will first discuss the feasibility and its meaning of applying some existing coverage metrics to Verilog-A code. We also propose a new coverage metric, frequency coverage, for checking the completeness of the frequency response in Verilog-A designs. Using this coverage metric as an assistant to existing code coverage metrics, we can have more confidence on the correctness of the Verilog-A descriptions at different situations.