Physical Verification at Advanced Technology Nodes and the Road Ahead

Abstract

In spite of "doomsday" expectations, Moore's Law is alive and well. Semiconductor manufacturing and design companies, as well as the Electronic Design Automation (EDA) industry have been pushing ahead to bring more functionality to satisfy more aggressive space/power/performance requirements. Physical verification occupies a unique space in the ecosystem as one of the key bridges between design and manufacturing. As such, the traditional space of design rule checking (DRC) and layout versus schematic (LVS) have expanded into electrical verification and yield enabling technologies such as optical proximity correction, critical area analysis, multi-patterning decomposition and automated filling. To achieve the expected accuracy and performance demanded by the design and manufacturing community, it is necessary to consider the physical effects of the manufacturing processes and electronic devices and to use the most advanced software engineering technology and computational capabilities.