Physical Verification at Advanced Technology Nodes and the Road Ahead

J. Rey
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Abstract

In spite of "doomsday" expectations, Moore's Law is alive and well. Semiconductor manufacturing and design companies, as well as the Electronic Design Automation (EDA) industry have been pushing ahead to bring more functionality to satisfy more aggressive space/power/performance requirements. Physical verification occupies a unique space in the ecosystem as one of the key bridges between design and manufacturing. As such, the traditional space of design rule checking (DRC) and layout versus schematic (LVS) have expanded into electrical verification and yield enabling technologies such as optical proximity correction, critical area analysis, multi-patterning decomposition and automated filling. To achieve the expected accuracy and performance demanded by the design and manufacturing community, it is necessary to consider the physical effects of the manufacturing processes and electronic devices and to use the most advanced software engineering technology and computational capabilities.
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先进技术节点的物理验证与未来道路
尽管有“世界末日”的预期,但摩尔定律仍然存在。半导体制造和设计公司,以及电子设计自动化(EDA)行业一直在推动带来更多的功能,以满足更大的空间/功率/性能要求。物理验证作为设计和制造之间的关键桥梁之一,在生态系统中占据着独特的空间。因此,传统的设计规则检查(DRC)和布局与原理图(LVS)的空间已经扩展到电气验证和使能技术,如光学接近校正、关键区域分析、多图案分解和自动填充。为了达到设计和制造界所要求的预期精度和性能,有必要考虑制造过程和电子设备的物理效应,并使用最先进的软件工程技术和计算能力。
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