Ming-Hung Chen, Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu
{"title":"Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design","authors":"Ming-Hung Chen, Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu","doi":"10.1109/BIBE.2019.00107","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new pair hidden Markov model (Pair-HMM) algorithm, namely Banded Pair-HMM, which is a heuristic approach for variant calling applications. When compared to the conventional Pair-HMM, our Banded Pair-HMM can reduce the execution time at a minor cost in accuracy. In addition, a hardware accelerator is implemented using TSMC 40nm technology based on the proposed algorithm. As demonstrated later in the paper, the proposed hardware accelerator runs 4× faster than the conventional Pair-HMM hardware, and over 17,000× faster than the original Pair-HMM software.","PeriodicalId":318819,"journal":{"name":"2019 IEEE 19th International Conference on Bioinformatics and Bioengineering (BIBE)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 19th International Conference on Bioinformatics and Bioengineering (BIBE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIBE.2019.00107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, we propose a new pair hidden Markov model (Pair-HMM) algorithm, namely Banded Pair-HMM, which is a heuristic approach for variant calling applications. When compared to the conventional Pair-HMM, our Banded Pair-HMM can reduce the execution time at a minor cost in accuracy. In addition, a hardware accelerator is implemented using TSMC 40nm technology based on the proposed algorithm. As demonstrated later in the paper, the proposed hardware accelerator runs 4× faster than the conventional Pair-HMM hardware, and over 17,000× faster than the original Pair-HMM software.