Selectable grained reconfigurable architecture (SGRA) and its design automation

Abstract

In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Block can be configured to operate in either fine-grained or coarse-grained mode. Compared with the Mixed Grained Reconfigurable Architecture (MGRA), which has a fixed ratio of fine- and coarse-grained operation blocks and a heterogeneous floorplan, SGRA offers greater flexibility in the mapping and placement of functional units, thus reducing wasted wiring and improving the critical path delay. We also present an automated design flow for SGRA that is developed by customizing the Verilog-to-Routing (VTR) platform. Experimental results demonstrate that SGRA achieves, on average, a 13% reduction in circuit area over MGRA.