Evaluation of clock distribution networks' most likely faults and produced effects

Abstract

Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor we evaluate the fault models that better describe the manufacturing defects that are most likely to affect signals of the clock distribution network. The probability of these faults has been estimated by means of Inductive Fault Analysis (IFA) and has been found to be, for the majority of cases, comparable if not one order of magnitude higher than that of other most likely microprocessor faults. The effects of the most likely clock faults has then been analyzed by means of electrical level simulations. Differently from what is generally implicitly assumed, we have found that only a small percentage of these faults results in a catastrophic failure of the microprocessor, thus being possibly easily detectable during manufacturing test, while the majority results in a local failure, which cannot be detected during manufacturing test, although compromising the microprocessor correct operation and causing an unacceptable decrease in its reliability.