S. Rachidi, S. Ramesh, L. Breuil, Z. Tao, D. Verreck, G. Donadio, A. Arreghini, G. V. D. Bosch, M. Rosmeulen
{"title":"Enabling 3D NAND Trench Cells for Scaled Flash Memories","authors":"S. Rachidi, S. Ramesh, L. Breuil, Z. Tao, D. Verreck, G. Donadio, A. Arreghini, G. V. D. Bosch, M. Rosmeulen","doi":"10.1109/IMW56887.2023.10145992","DOIUrl":null,"url":null,"abstract":"3D Trench cells with a vertical flat channel have been proposed to increase the cell density over 3D NAND gate-all-around (GAA). In this work, we investigate the device characteristics of Trench cells. In absence of curvature, Trench cells exhibit inferior program and erase in comparison to a GAA reference. However, the memory window of Trench cells is significantly improved with channel width scaling, gate stack engineering and metal gate integration. This study also provides a basis for design and fabrication of future ultradense 3D NAND memories based on the Trench architecture.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
3D Trench cells with a vertical flat channel have been proposed to increase the cell density over 3D NAND gate-all-around (GAA). In this work, we investigate the device characteristics of Trench cells. In absence of curvature, Trench cells exhibit inferior program and erase in comparison to a GAA reference. However, the memory window of Trench cells is significantly improved with channel width scaling, gate stack engineering and metal gate integration. This study also provides a basis for design and fabrication of future ultradense 3D NAND memories based on the Trench architecture.