Variability-and reliability-aware design for 16/14nm and beyond technology

Abstract

Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (Vdd). Therefore, robust design should have the awareness of both variability and reliability. In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure. Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation-and correlation-aware design. For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA). New-generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools. Future challenges are also pointed out, such as statistical BTI and RTN. The results are helpful for the robust and resilient design for 16/14nm and beyond.