Applications of closed-form wiring escape formulae to a high performance printed wiring board

Abstract

Closed-form formulae are derived for wiring escape from an area array to the standard horizontal ground rules of the package level under consideration. The required layer counts for successful escape based on two strategies are given in this paper. The effects of lines per channel, extra channels at the edges of an area array, different via technologies, and signal pin depopulation are considered in the derivations. The resulting closed-form formulae are also used to a high performance printed wiring board for the estimation of the layers needed. The estimation of the layer count from our formulae agrees with the one achieved empirically in the actual design.