Forming Patch Functions and Combinational Circuit Rectification

Abstract

Increasing chips complexity originates a problem of providing their 100% correct fabrication. During chip fabrication logical bugs may be detected, changes of specification may appear and so on. There are some ways of recovering chips to provide functioning we need. One of them is connected with using Engineering Change Order (ECO) technique. In the frame of this technique forming of patch functions is based on using internal nodes of implemented circuit Ci (circuit that has to be corrected). Methods are oriented to cut calculations of patch functions with using SAT and QBS solvers and cut overhead. Functions of implemented circuit Ci and specification circuit Cs, as a rule, are essentially different. Our approach is oriented to slight difference between specification circuit Cs and implemented circuit Ci. We suggest using special miter system represented by list of products with their special characteristics. Our approach does not demand using SAT and QBS solvers. For correction we use only inputs and outputs of implemented circuit Ci. In contrast with current approaches there is no need using internal nodes of the implemented circuit.