Low power storage exploration for H.263 video decoder

L. Nachtergaele, Francky Catthoory, Bhanu Kapoorz, S. Janssens, D. Moolenaar
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引用次数: 48

Abstract

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data transfer scheme in the specification and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst-case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment.
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H.263视频解码器的低功耗存储探索
我们使用H.263视频解码演示应用程序描述了数据主导应用程序的功率勘探方法。我们探索的起点是视频解码器的C规范,可从Telenor Research的公共领域获得。我们对规范中的数据传输方案进行了转换,并对分布式内存组织进行了优化。这将产生功耗显著降低的内存架构。对于使用预测和双向(PB)帧的最坏情况模式,内存功耗降低了9倍。为了实现这些结果,我们使用了我们的形式化高级内存管理方法,ATOMIUM环境部分支持这种方法。
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Real-time MPEG-2 software decoding with a dual-issue RISC processor A chip set for a ray-casting engine An object based data cache with conflict free concurrent access as shared memory for a parallel DSP A 500 MHz, one volt, 16 by 16 bit multiplier for DSP cores A parallel architecture for rapid prototyping of mechatronic algorithms by exploiting implicit fine-grain parallelism
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