Variation-aware Analog Circuit Sizing with Classifier Chains

Abstract

In this work, a simulation-based optimization framework is proposed that determines the sizing of components of an analog circuit to meet target design specifications while also satisfying the robustness specifications set by the designer. The robustness is guaranteed by setting a limit on the standard deviations of the variations in the performance parameters of a circuit across all process and temperature corners of interest. Classifier chains are utilized that, in addition to modeling the relationship between inputs and outputs, learn the relationships among output labels. Additional design knowledge is inferred from the optimal ordering of the classifier chain. A case study is provided, where an LNA is designed in a 65 nm fabrication process. The corners of interest include the combination of the three temperatures of 20°C, 80°C, and 120°C, and the five process corners of typical-typical, slow-slow, fast-fast, slow-fast, and fast-slow. The adoption of classifier chains and the ensemble of classifier chains provides an improvement in the prediction accuracy as compared to the utilization of binary relevance. A qualified design solution is generated that satisfies both the performance and robustness specifications within 5 executed iterations of the design loop.