Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531079
Shuyuan Yu, Yibo Liu, S. Tan
Stochastic computing (SC) promises extremely low cost and energy efficiency for error-tolerant arithmetic operations in many emerging applications such as image processing and deep neural networks. Existing SC-based nonlinear functions like division, however, require highly correlated bit-streams, which does not fit well with the existing SC computing framework in which randomness is required for accuracy. In this paper, we propose a novel SC-based divider design based on recently proposed counting-based stochastic computing scheme, which is much more accurate and faster than traditional SC, and does not depend on randomness of bit-streams for accuracy. We show how such counting-based SC can be applied to nonlinear functions like division. The new divider, called counting-based divider, or CBDIV, exploits both the correlation requirement of existing SC-based division methods and high efficiency of counting-based SC scheme. It essentially combines the best of two worlds in SC and the resulting division operation can be performed as a more efficient partial counting process. Experimental results show that the proposed CBDIV implemented in a 32nm technology node outperforms state of art works by 77.8% in accuracy, 37.1% in delay, 21.5% in area, 50.6% in ADP (area delay product) and 25.9% in power. CBDIV also saves 31.9% in energy consumption when compared to the fixed-point division baseline, and is much more energy efficient than existing SC-based dividers for binary inputs and outputs required in efficient image process implementations. Furthermore, CBDIV with 5-bit precision can even outperform state of art works with 7-bit precision in accuracy by 15.4%. Finally, we compare CBDIV with other state of art SC dividers in contrast stretch application and show that CBDIV can improve the accuracy with 20.6dB in average, which is a huge improvement.
{"title":"Approximate Divider Design Based on Counting-Based Stochastic Computing Division","authors":"Shuyuan Yu, Yibo Liu, S. Tan","doi":"10.1109/MLCAD52597.2021.9531079","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531079","url":null,"abstract":"Stochastic computing (SC) promises extremely low cost and energy efficiency for error-tolerant arithmetic operations in many emerging applications such as image processing and deep neural networks. Existing SC-based nonlinear functions like division, however, require highly correlated bit-streams, which does not fit well with the existing SC computing framework in which randomness is required for accuracy. In this paper, we propose a novel SC-based divider design based on recently proposed counting-based stochastic computing scheme, which is much more accurate and faster than traditional SC, and does not depend on randomness of bit-streams for accuracy. We show how such counting-based SC can be applied to nonlinear functions like division. The new divider, called counting-based divider, or CBDIV, exploits both the correlation requirement of existing SC-based division methods and high efficiency of counting-based SC scheme. It essentially combines the best of two worlds in SC and the resulting division operation can be performed as a more efficient partial counting process. Experimental results show that the proposed CBDIV implemented in a 32nm technology node outperforms state of art works by 77.8% in accuracy, 37.1% in delay, 21.5% in area, 50.6% in ADP (area delay product) and 25.9% in power. CBDIV also saves 31.9% in energy consumption when compared to the fixed-point division baseline, and is much more energy efficient than existing SC-based dividers for binary inputs and outputs required in efficient image process implementations. Furthermore, CBDIV with 5-bit precision can even outperform state of art works with 7-bit precision in accuracy by 15.4%. Finally, we compare CBDIV with other state of art SC dividers in contrast stretch application and show that CBDIV can improve the accuracy with 20.6dB in average, which is a huge improvement.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114945618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531300
Mohamed Saleh Abouelyazid, S. Hammouda, Y. Ismail
A novel neural-networks parasitic extraction modeling methodology for interconnect parasitic capacitances is developed in rule-based extractors. The current rule-based extractors rely on thousands of parasitic capacitance formulas, each covering few or very limited set of interconnect patterns. These formulas also typically suffer from large errors in corner cases. The proposed methodology provides compact cross-section neural-network models that predict parasitic coupling capacitances for many diverse metal arrangements considering metals connectivity. These models significantly improve the accuracy of rule-based extraction methods. Also, they significantly reduce the pattern mismatches in traditional rule-based methods. The inputs to the proposed compact models are: dimensions of a layout pattern, aggressor polygons, and the required victim polygons for a certain process stack. Two different pattern representations are proposed to be used as inputs to neural-networks models: ratio-based and dimensions-based representations. The proposed methodology shows superior characteristics as compared to traditional existing models in four ways. First, it has high pattern coverage. Second, it mitigates the pattern mismatches. Third, it provides compact, descriptive, and accurate cross-section parasitic models. Fourth, it can handle the increasing accuracy requirements in advanced nodes. The proposed methodology is tested over three test chips of 28nm process node with more than 4.8M interconnect structures. The proposed methodology managed to significantly reduce the pattern mismatches and provided outstanding results as compared to field-solvers with an average error < 0.1% and a standard deviation < 3.2%.
{"title":"Connectivity-Based Machine Learning Compact Models for Interconnect Parasitic Capacitances","authors":"Mohamed Saleh Abouelyazid, S. Hammouda, Y. Ismail","doi":"10.1109/MLCAD52597.2021.9531300","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531300","url":null,"abstract":"A novel neural-networks parasitic extraction modeling methodology for interconnect parasitic capacitances is developed in rule-based extractors. The current rule-based extractors rely on thousands of parasitic capacitance formulas, each covering few or very limited set of interconnect patterns. These formulas also typically suffer from large errors in corner cases. The proposed methodology provides compact cross-section neural-network models that predict parasitic coupling capacitances for many diverse metal arrangements considering metals connectivity. These models significantly improve the accuracy of rule-based extraction methods. Also, they significantly reduce the pattern mismatches in traditional rule-based methods. The inputs to the proposed compact models are: dimensions of a layout pattern, aggressor polygons, and the required victim polygons for a certain process stack. Two different pattern representations are proposed to be used as inputs to neural-networks models: ratio-based and dimensions-based representations. The proposed methodology shows superior characteristics as compared to traditional existing models in four ways. First, it has high pattern coverage. Second, it mitigates the pattern mismatches. Third, it provides compact, descriptive, and accurate cross-section parasitic models. Fourth, it can handle the increasing accuracy requirements in advanced nodes. The proposed methodology is tested over three test chips of 28nm process node with more than 4.8M interconnect structures. The proposed methodology managed to significantly reduce the pattern mismatches and provided outstanding results as compared to field-solvers with an average error < 0.1% and a standard deviation < 3.2%.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134154230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531153
J. Xiong, Alan Yang, M. Raginsky, E. Rosenbaum
Theoretical analyses as well as case studies have established that behavioral models based on a recurrent neural network (RNN) are suitable for transient modeling of nonlinear circuits. After training, an RNN model can be implemented in Verilog-A and evaluated by a SPICE-type circuit simulator. This paper describes hurdles that have prevented wide-scale adoption of the RNN as an IP-obscuring behavioral model for circuits and presents recent advances. A new stability constraint is formulated and demonstrated to guide model training and improve performance. Augmented RNNs that can accurately capture aging effects and represent process variations are presented.
{"title":"Neural Networks for Transient Modeling of Circuits : Invited Paper","authors":"J. Xiong, Alan Yang, M. Raginsky, E. Rosenbaum","doi":"10.1109/MLCAD52597.2021.9531153","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531153","url":null,"abstract":"Theoretical analyses as well as case studies have established that behavioral models based on a recurrent neural network (RNN) are suitable for transient modeling of nonlinear circuits. After training, an RNN model can be implemented in Verilog-A and evaluated by a SPICE-type circuit simulator. This paper describes hurdles that have prevented wide-scale adoption of the RNN as an IP-obscuring behavioral model for circuits and presents recent advances. A new stability constraint is formulated and demonstrated to guide model training and improve performance. Augmented RNNs that can accurately capture aging effects and represent process variations are presented.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128359107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531109
Luis Francisco, P. Franzon, W. R. Davis
The power, performance, and area (PPA) of a System-on-Chip (SoC) is known only after a months-long process. This process includes iterations over the architectural design, register transfer level implementation, RTL synthesis, and place and route. Knowing the PPA estimates for a system early in the design stages can help resolve tradeoffs that will affect the final design. This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the PPA. This work focuses on reducing the number of samples used to create the models. The models use transfer learning to predict the PPA for new design configurations and corner conditions based on previous models. The models predict the PPA as a function of parameters accessible during the RTL synthesis. The proposed models achieved PPA predictions up to 99% accurate and using as few as 10 data samples can achieve accuracies better than 96%.
{"title":"Fast and Accurate PPA Modeling with Transfer Learning","authors":"Luis Francisco, P. Franzon, W. R. Davis","doi":"10.1109/MLCAD52597.2021.9531109","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531109","url":null,"abstract":"The power, performance, and area (PPA) of a System-on-Chip (SoC) is known only after a months-long process. This process includes iterations over the architectural design, register transfer level implementation, RTL synthesis, and place and route. Knowing the PPA estimates for a system early in the design stages can help resolve tradeoffs that will affect the final design. This work presents a machine learning approach using gradient boost models and neural networks to fast and accurately predict the PPA. This work focuses on reducing the number of samples used to create the models. The models use transfer learning to predict the PPA for new design configurations and corner conditions based on previous models. The models predict the PPA as a function of parameters accessible during the RTL synthesis. The proposed models achieved PPA predictions up to 99% accurate and using as few as 10 data samples can achieve accuracies better than 96%.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121622218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531273
Zhengfeng Wu, I. Savidis
In this work, a simulation-based optimization framework is proposed that determines the sizing of components of an analog circuit to meet target design specifications while also satisfying the robustness specifications set by the designer. The robustness is guaranteed by setting a limit on the standard deviations of the variations in the performance parameters of a circuit across all process and temperature corners of interest. Classifier chains are utilized that, in addition to modeling the relationship between inputs and outputs, learn the relationships among output labels. Additional design knowledge is inferred from the optimal ordering of the classifier chain. A case study is provided, where an LNA is designed in a 65 nm fabrication process. The corners of interest include the combination of the three temperatures of 20°C, 80°C, and 120°C, and the five process corners of typical-typical, slow-slow, fast-fast, slow-fast, and fast-slow. The adoption of classifier chains and the ensemble of classifier chains provides an improvement in the prediction accuracy as compared to the utilization of binary relevance. A qualified design solution is generated that satisfies both the performance and robustness specifications within 5 executed iterations of the design loop.
{"title":"Variation-aware Analog Circuit Sizing with Classifier Chains","authors":"Zhengfeng Wu, I. Savidis","doi":"10.1109/MLCAD52597.2021.9531273","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531273","url":null,"abstract":"In this work, a simulation-based optimization framework is proposed that determines the sizing of components of an analog circuit to meet target design specifications while also satisfying the robustness specifications set by the designer. The robustness is guaranteed by setting a limit on the standard deviations of the variations in the performance parameters of a circuit across all process and temperature corners of interest. Classifier chains are utilized that, in addition to modeling the relationship between inputs and outputs, learn the relationships among output labels. Additional design knowledge is inferred from the optimal ordering of the classifier chain. A case study is provided, where an LNA is designed in a 65 nm fabrication process. The corners of interest include the combination of the three temperatures of 20°C, 80°C, and 120°C, and the five process corners of typical-typical, slow-slow, fast-fast, slow-fast, and fast-slow. The adoption of classifier chains and the ensemble of classifier chains provides an improvement in the prediction accuracy as compared to the utilization of binary relevance. A qualified design solution is generated that satisfies both the performance and robustness specifications within 5 executed iterations of the design loop.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122691208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531320
Subed Lamichhane, Shaoyi Peng, Wentian Jin, S. Tan
Electrostatic analysis, which computes electrical potential and electrical field, is important for VLSI reliability and high speed circuit design. Deep learning provides new opportunities and challenges to speedup the analysis process by learning physical laws and feature representations. In this work, we propose an image generative learning framework for electrostatic analysis for VLSI dielectric aging estimation. This work leverages the observation that the synthesized multi layer interconnect VLSI layout can be viewed as layered 2D images and the analysis can be viewed as the image generation. The efficient image-to-image translation property of generative learning is therefore used to obtain the potential distribution on the respective interconnect layers. Compared with the recent CNN-based electrostatic analysis method, the new method can lead to 1.54x speedup for inference due to reduced neural network structures and parameters. We demonstrate the proposed method for time-dependent dielectric breakdown analysis and show the significant speedup compared to the traditional numerical method.
{"title":"Fast Electrostatic Analysis For VLSI Aging based on Generative Learning","authors":"Subed Lamichhane, Shaoyi Peng, Wentian Jin, S. Tan","doi":"10.1109/MLCAD52597.2021.9531320","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531320","url":null,"abstract":"Electrostatic analysis, which computes electrical potential and electrical field, is important for VLSI reliability and high speed circuit design. Deep learning provides new opportunities and challenges to speedup the analysis process by learning physical laws and feature representations. In this work, we propose an image generative learning framework for electrostatic analysis for VLSI dielectric aging estimation. This work leverages the observation that the synthesized multi layer interconnect VLSI layout can be viewed as layered 2D images and the analysis can be viewed as the image generation. The efficient image-to-image translation property of generative learning is therefore used to obtain the potential distribution on the respective interconnect layers. Compared with the recent CNN-based electrostatic analysis method, the new method can lead to 1.54x speedup for inference due to reduced neural network structures and parameters. We demonstrate the proposed method for time-dependent dielectric breakdown analysis and show the significant speedup compared to the traditional numerical method.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117297625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531243
T. Martin, S. Areibi, G. Grewal
The ability to efficiently and accurately predict placement routability, while avoiding the large computational cost of performing routing, is an asset when seeking to reduce total placement and routing runtime. In this paper, we present a series of simple ML models and ensembles to predict the routability of a placement solution. Ensembles based on Bagging, Boosting and Stack of classifiers are introduced to produce more accurate and robust solutions than single/simple models. Our results show an improvement in prediction accuracy and runtime compared to the best published results in the literature.
{"title":"Effective Machine-Learning Models for Predicting Routability During FPGA Placement","authors":"T. Martin, S. Areibi, G. Grewal","doi":"10.1109/MLCAD52597.2021.9531243","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531243","url":null,"abstract":"The ability to efficiently and accurately predict placement routability, while avoiding the large computational cost of performing routing, is an asset when seeking to reduce total placement and routing runtime. In this paper, we present a series of simple ML models and ensembles to predict the routability of a placement solution. Ensembles based on Bagging, Boosting and Stack of classifiers are introduced to produce more accurate and robust solutions than single/simple models. Our results show an improvement in prediction accuracy and runtime compared to the best published results in the literature.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121438209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531284
Madhvi Agarwal, Sneh Saurabh
Traditionally, the timing model of a flip-flop in the technology libraries captures the setup time (ST), hold time (HT) and clock-to-q (C2Q) delays in separate two-dimensional lookup tables. However, it is well-known that these attributes of flip-flops are interdependent. By modeling them separately we introduce pessimism in the design flows. In this paper, we represent the C2Q delays of a flip-flop using artificial neural networks (ANN) and store them in technology libraries. The ANN captures the dependency of the C2Q delay on the data slew, clock slew, output load, setup skew and hold skew. We show that the proposed model computes the C2Q delays with errors less than 3% compared to the SPICE model. Furthermore, using 65 nm foundry library and 15 nm NCSU FreePDK15 models, we demonstrate the effectiveness of the proposed model in removing pessimism of the traditional flip-flop timing model. Additionally, we can employ it to transfer the surplus slack on the output side of a flip-flop to the input side. Thus, we can filter out marginal timing violations and alleviate the timing closure problem using the proposed model.
{"title":"An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network","authors":"Madhvi Agarwal, Sneh Saurabh","doi":"10.1109/MLCAD52597.2021.9531284","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531284","url":null,"abstract":"Traditionally, the timing model of a flip-flop in the technology libraries captures the setup time (ST), hold time (HT) and clock-to-q (C2Q) delays in separate two-dimensional lookup tables. However, it is well-known that these attributes of flip-flops are interdependent. By modeling them separately we introduce pessimism in the design flows. In this paper, we represent the C2Q delays of a flip-flop using artificial neural networks (ANN) and store them in technology libraries. The ANN captures the dependency of the C2Q delay on the data slew, clock slew, output load, setup skew and hold skew. We show that the proposed model computes the C2Q delays with errors less than 3% compared to the SPICE model. Furthermore, using 65 nm foundry library and 15 nm NCSU FreePDK15 models, we demonstrate the effectiveness of the proposed model in removing pessimism of the traditional flip-flop timing model. Additionally, we can employ it to transfer the surplus slack on the output side of a flip-flop to the input side. Thus, we can filter out marginal timing violations and alleviate the timing closure problem using the proposed model.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132424400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531210
M. Alawieh, D. Pan
Recent advances in machine learning have introduced a new lens to envision novel solutions in many research domains and the Electronic Design Automation field is an evident example. Today, Machine Learning research is penetrating into the different stages of the Integrated Circuits design cycles equipped with accurate and fast models. However, addressing the applicability of learned models within the ever-changing design environment has not received enough study. In this work, we propose ADAPT as a framework for the fast migration of machine learning models. Towards this end, an unsupervised Bayesian-based accuracy estimation method is used. Moreover, different techniques for learning with small datasets are adopted to build a complete migration framework. The efficacy of ADAPT, both in terms of accelerating model migration and accurate estimations, is demonstrated by using lithography hotspot detection as a case study.
{"title":"ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection","authors":"M. Alawieh, D. Pan","doi":"10.1109/MLCAD52597.2021.9531210","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531210","url":null,"abstract":"Recent advances in machine learning have introduced a new lens to envision novel solutions in many research domains and the Electronic Design Automation field is an evident example. Today, Machine Learning research is penetrating into the different stages of the Integrated Circuits design cycles equipped with accurate and fast models. However, addressing the applicability of learned models within the ever-changing design environment has not received enough study. In this work, we propose ADAPT as a framework for the fast migration of machine learning models. Towards this end, an unsupervised Bayesian-based accuracy estimation method is used. Moreover, different techniques for learning with small datasets are adopted to build a complete migration framework. The efficacy of ADAPT, both in terms of accelerating model migration and accurate estimations, is demonstrated by using lithography hotspot detection as a case study.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114739493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-30DOI: 10.1109/MLCAD52597.2021.9531156
Yaguang Li, Yishuang Lin, Meghna Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, Jiang Hu
Analog integrated circuit design is highly complex and its automation is a long-standing challenge. We present a reinforcement learning approach to automatic transistor sizing, a key step in determining analog circuit performance. A circuit attention network technique is developed to capture the impact of transistor sizing on circuit performance in an actor-critic learning framework. Our approach also includes a stochastic technique for addressing layout effect, another important factor affecting performance. Compared to Bayesian optimization (BO) and Graph Convolutional Network-based reinforcement learning (GCN-RL), two state-of-the-art methods, the proposed approach significantly improves robustness against layout uncertainty while achieving better post-layout performance. BO and GCN-RL can be enhanced with our stochastic technique to reach solution quality similar to ours, but still suffer from a much slower convergence rate. Moreover, the knowledge transfer in our approach is more effective than that in GCN-RL.
{"title":"A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing","authors":"Yaguang Li, Yishuang Lin, Meghna Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, Jiang Hu","doi":"10.1109/MLCAD52597.2021.9531156","DOIUrl":"https://doi.org/10.1109/MLCAD52597.2021.9531156","url":null,"abstract":"Analog integrated circuit design is highly complex and its automation is a long-standing challenge. We present a reinforcement learning approach to automatic transistor sizing, a key step in determining analog circuit performance. A circuit attention network technique is developed to capture the impact of transistor sizing on circuit performance in an actor-critic learning framework. Our approach also includes a stochastic technique for addressing layout effect, another important factor affecting performance. Compared to Bayesian optimization (BO) and Graph Convolutional Network-based reinforcement learning (GCN-RL), two state-of-the-art methods, the proposed approach significantly improves robustness against layout uncertainty while achieving better post-layout performance. BO and GCN-RL can be enhanced with our stochastic technique to reach solution quality similar to ours, but still suffer from a much slower convergence rate. Moreover, the knowledge transfer in our approach is more effective than that in GCN-RL.","PeriodicalId":210763,"journal":{"name":"2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116507604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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