A CMOS-based logic cell for the implementation of self-checking FPGAs

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI:10.1109/DFTVS.1999.802890

P. Lala, Anup Singh, A. Walker

引用次数: 5

Abstract

This paper proposes a logic cell that can be used as a building block for online testable FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch (DCVS) logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexer and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults or identical outputs in the presence of fault.

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一种用于实现自检fpga的基于cmos的逻辑单元

本文提出了一种逻辑单元，可以作为在线可测试fpga的构建块。所提出的逻辑单元由两个2对1多路复用器、三个4对1多路复用器和一个D触发器组成。该单元采用差分级联电压开关(DCVS)逻辑设计。它对所有单晶体管卡通和卡关故障以及每个多路复用器和D触发器的输入卡通故障都具有自检功能。多路复用器和D触发器在没有上述故障时提供正确(互补)输出或在存在故障时提供相同输出。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

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