S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos
{"title":"A 64Kb CMOS EEROM with on-chip ECC","authors":"S. Mehrotra, Tsung-Ching Wu, Te-Long Chiu, G. Perlegos","doi":"10.1109/ISSCC.1984.1156662","DOIUrl":null,"url":null,"abstract":"A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm<sup>2</sup>two-transistor cell and 33100 mil<sup>2</sup>die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm2two-transistor cell and 33100 mil2die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.
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