PALACE: a layout generator for SCVS logic blocks

Abstract

A novel approach to the automatic layout synthesis of dynamic CMOS circuits is presented. A set of logic expressions is realized in a row of cells. Taking multi-level Boolean expressions as input, logic transistors are placed and routed. Efficient solutions are achieved by permitting the variables of the expressions and by row folding. The layout is designed on a coarse grid taking timing requirements into account and afterwards adapted to the geometric design rules by a compactor. A comparison to handcrafted layouts shows that the results of PALACE are nearly equivalent, while the design productivity is significantly increased.<>