A 1 GHz Pipelined Low Power Floating Point Arithmetic Unit with Modified Scheduling for High Speed Applications

Abstract

This paper proposes an architecture for a pipelined 1 GHz floating point arithmetic unit incorporated with the concept of modified dynamic scheduling which enables the unit to accept an input instruction every clock cycle until there is an output clash, in which case the outputs are sent out based on the first in first out concept. The architecture proposed has three independent functional units, which can be issued with instructions either one at a time using a small control word or in parallel using a large control word based on the dependency of input operations. The entire design has been simulated using Cadence NcSim. Synthesis and advanced flows such as low power, design for testability and multi Vt flows have been carried out with Cadence RTL compiler to ensure low power and maximum frequency of operation