J. Bao, X. Du, M. Shirokov, R. Leoni, J.C.M. Hwang
{"title":"Substrate-induced gate lag in ion-implanted GaAs MESFETs","authors":"J. Bao, X. Du, M. Shirokov, R. Leoni, J.C.M. Hwang","doi":"10.1109/GAAS.1997.628260","DOIUrl":null,"url":null,"abstract":"Gate lag in ion-implanted GaAs MESFETs has been investigated by using a novel pulsed S-parameter/waveform measurement technique. The results indicate that, for the present devices, gate lag is mainly caused by substrate-trap-induced threshold-voltage shift. Since these traps are required to ensure the substrate is semi-insulating, effective channel/substrate isolation is crucial for minimizing gate lag of these devices. The same technique can be used to assess the relative importance of surface vs. substrate traps to other types of devices and to help optimize their structures.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1997.628260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Gate lag in ion-implanted GaAs MESFETs has been investigated by using a novel pulsed S-parameter/waveform measurement technique. The results indicate that, for the present devices, gate lag is mainly caused by substrate-trap-induced threshold-voltage shift. Since these traps are required to ensure the substrate is semi-insulating, effective channel/substrate isolation is crucial for minimizing gate lag of these devices. The same technique can be used to assess the relative importance of surface vs. substrate traps to other types of devices and to help optimize their structures.