Enhanced concurrent error correcting arithmetic unit design using alternating logic

T. Ngai, E. Swartzlander, Chen He
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引用次数: 9

Abstract

Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.
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采用交替逻辑的增强型并发纠错算法单元设计
提出了一种基于时间共享三模冗余(TMR)技术的改进并发纠错算法单元设计方法。在交替逻辑的帮助下,这种新的设计方法将产生更高的可靠性,即100%的卡在故障可以被检测到,适度的硬件延迟和开销。基本思想是在算术单元的前后添加逆变器和多路复用器,并让一些控制逻辑选择数据的路径。这种设计方法可以应用于任何具有硬件冗余的系统。为了演示和比较,设计并验证了16位VLSI纹波进位加法器,采用分时TMR技术和分时TMR交替逻辑策略。仿真结果表明,该方法具有较高的可靠性,仅增加了少量的硬件延迟。
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