Defect density assessment in an integrated circuit fabrication line

Abstract

Two complementary approaches used to detect and quantify defects in a wafer fabrication line are described. The first approach uses data from the automated inspection of wafers. Defects that are likely to become electrical faults are identified and classified with the aid of a KLA 2020 inspection system. The second approach uses electrical fault data from the automated testing of defect test structures. The defects responsible for the faults are classified by visual inspection. This paper describes the models used to report the data from each of these sources. A clustering model is used in both cases to report the data as a defect density or a limited yield. Examples show the use of these reports to guide yield improvement activities in a production wafer fabrication facility.<>