Exploiting wafer level packaging of VCSELs on silicon photonic integrated circuits (PICs) with the advantages of a novel, flip-chip bonding, active dry-alignments method on SOI up-reflecting mirrors (Conference Presentation)
{"title":"Exploiting wafer level packaging of VCSELs on silicon photonic integrated circuits (PICs) with the advantages of a novel, flip-chip bonding, active dry-alignments method on SOI up-reflecting mirrors (Conference Presentation)","authors":"G. Delrosso","doi":"10.1117/12.2633800","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":210979,"journal":{"name":"Optical System Alignment, Tolerancing, and Verification XIV","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Optical System Alignment, Tolerancing, and Verification XIV","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2633800","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}