RF performance projections for 2D graphene transistors: Role of parasitics at the ballistic transport limit

Pei Zhao, D. Jena, S. Koswatta
{"title":"RF performance projections for 2D graphene transistors: Role of parasitics at the ballistic transport limit","authors":"Pei Zhao, D. Jena, S. Koswatta","doi":"10.1109/DRC.2011.5994422","DOIUrl":null,"url":null,"abstract":"The modeled device structures are shown in Figure 1, (a) top-gated structure ε<inf>ox</inf> = 20 and t<inf>ox</inf> = 1.5nm, and (b) back-gated structure with 90nm thick SiO<inf>2</inf>. The contact resistance and parasitic capacitance have also been taken into consideration in the simulations. Figure 2 shows the effect of M-G contacts on the transfer characteristics and transconductance, g<inf>m</inf> for the top-gated structure. The on-current, I<inf>on</inf>, can be increased with strong M-G coupling strength Δ or heavy contact induced doping (i.e. larger ΔE<inf>contact</inf>). The off-current, I<inf>off</inf>, does not increase. Large ΔE<inf>contact</inf> increases g<inf>m</inf>, but the maximum g<inf>m</inf> does not show a strong dependence on Δ. We use Δ=50meV and ΔE<inf>contac</inf> = −0.4eV for rest of the simulations. Figure 3 shows the I<inf>DS</inf> vs. V<inf>GS</inf> and g<inf>m</inf> vs. V<inf>GS</inf> at different V<inf>DS</inf> for the top-gated structure. Large V<inf>DS</inf> yields a higher maximum g<inf>m</inf>, but low V<inf>DS</inf> shows better linearity with a broader ƒ<inf>T</inf> peak. Transfer characteristics with different channel lengths are shown in Figure 4. For the top-gated structure excellent gate electrostatics helps avoid short channel effects (SCE). I<inf>on</inf> remains the same for all channel lengths. I<inf>off</inf> increases about 1.5 times when L<inf>ch</inf> decreases from 100nm to 15nm due to direct source to drain tunneling. The rise in I<inf>off</inf> leads to g<inf>m</inf> degradation at L<inf>ch</inf>=15nm. In the back-gated structure, the on/off ratio is degraded at shorter channel lengths, and the minimum conduction point shifts. Figure 5 shows the effect of contact resistance on I<inf>D</inf> - V<inf>GS</inf> characteristics at L<inf>ch</inf> = 100nm. At V<inf>DS</inf> = 0.3V, compared with the intrinsic case, when R<inf>S/D</inf> = 0.5Ωmm, on/off ratio decreases 3x for the top-gated structure and 1.2x for the back-gated structure. I<inf>on</inf> reduces 22x for the top-gated structure and 6x for the back-gated structure. Figure 6 shows the comparison of ƒ<inf>T</inf> -V<inf>GS</inf> with different channel lengths at V<inf>DS</inf> = 0.3V. The cutoff frequency is calculated as ƒ<inf>T</inf> = 1/2πτ<inf>tot</inf>, where τ<inf>tot</inf> = L<inf>ch</inf>C<inf>gs</inf>/g<inf>m</inf> + C<inf>gd</inf>/g<inf>m</inf> + C<inf>gd</inf>(R<inf>S</inf>+R<inf>D</inf>), C<inf>gs</inf> = ∂Q<inf>ch</inf>/∂V<inf>GS</inf>, R<inf>S/D</inf> = 0.5Ωmm, and C<inf>gd</inf> = 2pF/cm and 0.5pF/cm for the top-gated and the back-gated structures, respectively. Charging/discharging process is faster at shorter channel lengths, thus the peak ƒ<inf>T</inf> increases. In the back-gated structure, SCE is strong, thus the on/off ratio decreases and g<inf>m</inf> drops dramatically at short L<inf>ch</inf>. When L<inf>ch</inf> is shorter than 30nm, even the peak ƒ<inf>T</inf> drops. Figure 7 summarizes the ƒ<inf>T</inf> vs. L<inf>ch</inf> at V<inf>DS</inf> = 0.3V. The intrinsic ƒ<inf>T</inf> = &#60;v>/2πL<inf>ch</inf> is added as a reference with the average ballistic velocity &#60;v> = 2v<inf>F</inf>/π in 2D graphene. With R<inf>S/D</inf> = 0.5Ωmm and C<inf>gd</inf> = 2pF/cm, ƒ<inf>T</inf> drops 2x at L<inf>ch</inf>=100nm and 8x and L<inf>ch</inf>=15nm for the top-gated structure. For the back-gated structure, with R<inf>S/D</inf> = 0.5Ωmm and C<inf>gd</inf> = 0.5pF/cm, when L<inf>ch</inf> is below 70nm, ƒ<inf>T</inf> does not increase, and it even decreases when the channel length is below 30nm. Thus, parasitics currently dominate the performance, and major gains are expected with their reduction. This work is supported by the Semiconductor Research Corporation Nanoelectronics Research Initiative and the National Institute of Standards and Technology through the Midwest Institute for Nanoelectronics Discovery (MIND).","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"69th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2011.5994422","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

The modeled device structures are shown in Figure 1, (a) top-gated structure εox = 20 and tox = 1.5nm, and (b) back-gated structure with 90nm thick SiO2. The contact resistance and parasitic capacitance have also been taken into consideration in the simulations. Figure 2 shows the effect of M-G contacts on the transfer characteristics and transconductance, gm for the top-gated structure. The on-current, Ion, can be increased with strong M-G coupling strength Δ or heavy contact induced doping (i.e. larger ΔEcontact). The off-current, Ioff, does not increase. Large ΔEcontact increases gm, but the maximum gm does not show a strong dependence on Δ. We use Δ=50meV and ΔEcontac = −0.4eV for rest of the simulations. Figure 3 shows the IDS vs. VGS and gm vs. VGS at different VDS for the top-gated structure. Large VDS yields a higher maximum gm, but low VDS shows better linearity with a broader ƒT peak. Transfer characteristics with different channel lengths are shown in Figure 4. For the top-gated structure excellent gate electrostatics helps avoid short channel effects (SCE). Ion remains the same for all channel lengths. Ioff increases about 1.5 times when Lch decreases from 100nm to 15nm due to direct source to drain tunneling. The rise in Ioff leads to gm degradation at Lch=15nm. In the back-gated structure, the on/off ratio is degraded at shorter channel lengths, and the minimum conduction point shifts. Figure 5 shows the effect of contact resistance on ID - VGS characteristics at Lch = 100nm. At VDS = 0.3V, compared with the intrinsic case, when RS/D = 0.5Ωmm, on/off ratio decreases 3x for the top-gated structure and 1.2x for the back-gated structure. Ion reduces 22x for the top-gated structure and 6x for the back-gated structure. Figure 6 shows the comparison of ƒT -VGS with different channel lengths at VDS = 0.3V. The cutoff frequency is calculated as ƒT = 1/2πτtot, where τtot = LchCgs/gm + Cgd/gm + Cgd(RS+RD), Cgs = ∂Qch/∂VGS, RS/D = 0.5Ωmm, and Cgd = 2pF/cm and 0.5pF/cm for the top-gated and the back-gated structures, respectively. Charging/discharging process is faster at shorter channel lengths, thus the peak ƒT increases. In the back-gated structure, SCE is strong, thus the on/off ratio decreases and gm drops dramatically at short Lch. When Lch is shorter than 30nm, even the peak ƒT drops. Figure 7 summarizes the ƒT vs. Lch at VDS = 0.3V. The intrinsic ƒT = <v>/2πLch is added as a reference with the average ballistic velocity <v> = 2vF/π in 2D graphene. With RS/D = 0.5Ωmm and Cgd = 2pF/cm, ƒT drops 2x at Lch=100nm and 8x and Lch=15nm for the top-gated structure. For the back-gated structure, with RS/D = 0.5Ωmm and Cgd = 0.5pF/cm, when Lch is below 70nm, ƒT does not increase, and it even decreases when the channel length is below 30nm. Thus, parasitics currently dominate the performance, and major gains are expected with their reduction. This work is supported by the Semiconductor Research Corporation Nanoelectronics Research Initiative and the National Institute of Standards and Technology through the Midwest Institute for Nanoelectronics Discovery (MIND).
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二维石墨烯晶体管的射频性能预测:弹道输运极限下寄生的作用
模型器件结构如图1所示,(a)顶部门控结构εox = 20, tox = 1.5nm, (b)背面门控结构,厚度为90nm SiO2。仿真中还考虑了接触电阻和寄生电容。图2显示了M-G触点对顶部门控结构的传递特性和跨导的影响。通过强M-G耦合强度Δ或重接触诱导掺杂(即更大的ΔEcontact),可以增加导通电流Ion。断开电流Ioff不增加。较大的ΔEcontact使gm增大,但最大gm对Δ的依赖性不强。我们使用Δ=50meV和ΔEcontac =−0.4eV进行其余的模拟。图3显示了顶门控结构在不同VDS下的IDS vs. VGS和gm vs. VGS。较大的VDS产生较高的最大gm,但较低的VDS具有较宽的ƒT峰,线性较好。不同通道长度的传输特性如图4所示。top-gated结构良好的静电学门有助于避免短沟道效应(SCE)。对于所有信道长度,离子保持不变。当Lch从100nm减小到15nm时,由于源-漏直接隧穿,Ioff增加了约1.5倍。在Lch=15nm处,Ioff的增加导致了gm的降解。在背门控结构中,在较短的通道长度下,通/关比降低,最小导通点移位。图5显示了Lch = 100nm时接触电阻对ID - VGS特性的影响。在VDS = 0.3V时,RS/D = 0.5Ωmm时,顶门控结构的通断比减小了3x,背门控结构的通断比减小了1.2x。离子对顶门控结构减少22x,对背门控结构减少6x。图6为在VDS = 0.3V时,ƒT -VGS在不同通道长度下的对比。截止频率计算公式为ƒT = 1/2πτtot,其中τtot = LchCgs/gm + Cgd/gm + Cgd(RS+RD), Cgs =∂Qch/∂VGS, RS/D = 0.5Ωmm,顶门控和背门控结构的截止频率分别为2pF/cm和0.5pF/cm。在较短的通道长度下,充放电过程更快,因此峰值ƒT增加。在背门控结构中,SCE较强,因此开关比减小,gm在短时间内急剧下降。当Lch小于30nm时,峰值ƒT也下降。图7总结了在VDS = 0.3V时ƒT与Lch的对比。以二维石墨烯中平均弹道速度<v> = 2vF/π为参照物,加入本征速度ƒT = <v> = 2vF/π。RS/D = 0.5Ωmm, Cgd = 2pF/cm时,ƒT在Lch=100nm处下降2x,在Lch=15nm处下降8x。对于背门控结构,当RS/D = 0.5Ωmm, Cgd = 0.5pF/cm时,当Lch小于70nm时,ƒT不增加,当通道长度小于30nm时,ƒT甚至减小。因此,寄生现象目前主导着性能,随着它们的减少,预计将取得重大进展。这项工作是由半导体研究公司纳米电子研究计划和国家标准与技术研究所通过中西部纳米电子发现研究所(MIND)支持的。
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