Pub Date : 2018-09-01DOI: 10.23919/eusipco.2018.8553324
Ruchi Misra, Chetan Kulkarni, Alok Kumar
: The complexity of chips for basestations for 5G and beyond is driving verification challenges. We will discuss some of the approaches to overcome the challenges and will also talk about the support which is needed from the EDA suppliers
{"title":"Technical program committee","authors":"Ruchi Misra, Chetan Kulkarni, Alok Kumar","doi":"10.23919/eusipco.2018.8553324","DOIUrl":"https://doi.org/10.23919/eusipco.2018.8553324","url":null,"abstract":": The complexity of chips for basestations for 5G and beyond is driving verification challenges. We will discuss some of the approaches to overcome the challenges and will also talk about the support which is needed from the EDA suppliers","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115838294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/drc.2009.5354881
K. Bernstein, M. Nagata, M.-R. Lin, Y. Omura, K. Sakamoto, J. Graham, K. Saraswat
{"title":"Rump sessions","authors":"K. Bernstein, M. Nagata, M.-R. Lin, Y. Omura, K. Sakamoto, J. Graham, K. Saraswat","doi":"10.1109/drc.2009.5354881","DOIUrl":"https://doi.org/10.1109/drc.2009.5354881","url":null,"abstract":"","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.6086644
S. Krishnamoorthy, P. Park, S. Rajan
We report on the design, fabrication, and characterization of the first interband tunnel junctions showing forward tunneling characteristics in the III-Nitride system. We have achieved record forward tunneling currents (>100 mA/cm2 at 10 mV, and > 10 A/cm2 peak current) using polarization engineered GaN/InGaN/GaN heterojunction diodes. We also report for the first time, negative differential resistance in interband III-Nitride tunnel junctions, with peak-valley current ratio (PVCR) of up to 5 at room temperature, and 147 at low temperature. Interband tunnel junctions can be utilized to connect multiple active regions devices such as multiple active region emitters and multi junction solar cells, which require efficient reverse tunneling and forward tunneling respectively. Efficient inter-band tunneling has been a challenge in III-Nitrides mainly due to the large band gaps found in this material system, which reduce tunneling probability. Recently, the unique property of polarization in III-nitrides was used to engineer band bending over smaller distances in nitride heterostructures to enhance tunneling [1, 2, 3], and we recently demonstrated a p-GaN/InGaN/n-GaN backward diode with record current density of 118 A/ cm2 at a reverse bias of 1 V where a thin high indium composition InGaN well was used to enhance tunneling between GaN regions [3]. Tunnel junctions are a critical component of multiple junction solar cells, and there is an interest to exploit the large band gap range of III-nitrides in such devices. However, such an application would require forward, rather than reverse tunnel diodes. In this work, we use polarization engineering to design and demonstrate the inter-band forward tunneling diodes with the high current density and low forward voltage drop.
{"title":"III-nitride tunnel diodes with record forward tunnel current density","authors":"S. Krishnamoorthy, P. Park, S. Rajan","doi":"10.1109/DRC.2011.6086644","DOIUrl":"https://doi.org/10.1109/DRC.2011.6086644","url":null,"abstract":"We report on the design, fabrication, and characterization of the first interband tunnel junctions showing forward tunneling characteristics in the III-Nitride system. We have achieved record forward tunneling currents (>100 mA/cm2 at 10 mV, and > 10 A/cm2 peak current) using polarization engineered GaN/InGaN/GaN heterojunction diodes. We also report for the first time, negative differential resistance in interband III-Nitride tunnel junctions, with peak-valley current ratio (PVCR) of up to 5 at room temperature, and 147 at low temperature. Interband tunnel junctions can be utilized to connect multiple active regions devices such as multiple active region emitters and multi junction solar cells, which require efficient reverse tunneling and forward tunneling respectively. Efficient inter-band tunneling has been a challenge in III-Nitrides mainly due to the large band gaps found in this material system, which reduce tunneling probability. Recently, the unique property of polarization in III-nitrides was used to engineer band bending over smaller distances in nitride heterostructures to enhance tunneling [1, 2, 3], and we recently demonstrated a p-GaN/InGaN/n-GaN backward diode with record current density of 118 A/ cm2 at a reverse bias of 1 V where a thin high indium composition InGaN well was used to enhance tunneling between GaN regions [3]. Tunnel junctions are a critical component of multiple junction solar cells, and there is an interest to exploit the large band gap range of III-nitrides in such devices. However, such an application would require forward, rather than reverse tunnel diodes. In this work, we use polarization engineering to design and demonstrate the inter-band forward tunneling diodes with the high current density and low forward voltage drop.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115134599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994486
W. Haensch
A scaling path for Si based technology seems possible to the 8nm node. Power limitation will force to reduce the supply voltage at the expense of device performance and susceptibility to process variations. A lower limit of Vdd=0.5V seems feasible. Parallelism on system level will provide system through put which stresses architecture and software development. In particular legacy code will be a problem for a transition period that might require dual supply multi core architectures. In this scenario device technology has to cater to both high voltage and low voltage operation. Beyond the 8nm node new device concepts are needed. Considering the time frame of a 2019 manufacturing for this node a device has to be demonstrated now. At this point CNTs seem to be the only viable option for the post Si area.
{"title":"Devices for high performance computing beyond 14nm node - is there anything other than Si?","authors":"W. Haensch","doi":"10.1109/DRC.2011.5994486","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994486","url":null,"abstract":"A scaling path for Si based technology seems possible to the 8nm node. Power limitation will force to reduce the supply voltage at the expense of device performance and susceptibility to process variations. A lower limit of Vdd=0.5V seems feasible. Parallelism on system level will provide system through put which stresses architecture and software development. In particular legacy code will be a problem for a transition period that might require dual supply multi core architectures. In this scenario device technology has to cater to both high voltage and low voltage operation. Beyond the 8nm node new device concepts are needed. Considering the time frame of a 2019 manufacturing for this node a device has to be demonstrated now. At this point CNTs seem to be the only viable option for the post Si area.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117129503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994532
M. Urteaga, R. Pierson, P. Rowell, V. Jain, E. Lobisser, M. Rodwell
We report results from a 130nm Indium Phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A 0.13×2µm2 transistor exhibits a current gain cutoff frequency ft >520GHz, with a simultaneous extrapolated power gain cutoff frequency fmax>1.1THz. The HBTs exhibit these RF figures-of-merit while maintaining a common-emitter breakdown voltage BVCEO=3.5V (JE=10µA/µm2). Additionally, scaling of the emitter junction length to 2µm enables high device performance at low total power levels. Transistors in the InGaAs/InP material system have demonstrated the highest reported transistor RF figures-of-merit. Previous published results include strained-InGaAs channel high-electron mobility transistors (HEMTs) with fmax of >1THz [1,2], and InP DHBTs with fmax >800GHz [3]. High bandwidth DHBTs have applications in a number of RF and mixed-signal applications due to their high power handling and high levels of integration relative to HEMTs. The HBTs reported in this work are designed for transceiver applications at the lower end of the THz frequency band [0.3–3 THz].
{"title":"130nm InP DHBTs with ft >0.52THz and fmax >1.1THz","authors":"M. Urteaga, R. Pierson, P. Rowell, V. Jain, E. Lobisser, M. Rodwell","doi":"10.1109/DRC.2011.5994532","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994532","url":null,"abstract":"We report results from a 130nm Indium Phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A 0.13×2µm<sup>2</sup> transistor exhibits a current gain cutoff frequency ft >520GHz, with a simultaneous extrapolated power gain cutoff frequency f<inf>max</inf>>1.1THz. The HBTs exhibit these RF figures-of-merit while maintaining a common-emitter breakdown voltage BV<inf>CEO</inf>=3.5V (J<inf>E</inf>=10µA/µm<sup>2</sup>). Additionally, scaling of the emitter junction length to 2µm enables high device performance at low total power levels. Transistors in the InGaAs/InP material system have demonstrated the highest reported transistor RF figures-of-merit. Previous published results include strained-InGaAs channel high-electron mobility transistors (HEMTs) with f<inf>max</inf> of >1THz [1,2], and InP DHBTs with f<inf>max</inf> >800GHz [3]. High bandwidth DHBTs have applications in a number of RF and mixed-signal applications due to their high power handling and high levels of integration relative to HEMTs. The HBTs reported in this work are designed for transceiver applications at the lower end of the THz frequency band [0.3–3 THz].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117348389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994499
Guangle Zhou, Y. Lu, R. Li, Q. Zhang, W. Hwang, Q. Liu, T. Vasen, H. Zhu, J. Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing
Tunnel field-effect transistors (TFETs) are under intense investigation for low-power applications because of their potential for extremely low subthreshold swing (SS) and low off-state leakage [1]. III–V semiconductors with small effective mass and near broken band alignment are considered to be ideal for TFETs in that they promise high on-current and ION/IOFF ratios [2–3]. In this paper, we report the first demonstration of an InAs/Al0.45Ga0.55Sb heterojunction TFETs fabricated using an optical-lithography-only, self-aligned process and also investigate the effects limiting the InAs/Al0.45Ga0.55Sb TFET performance.
{"title":"Self-aligned InAs/Al0.45Ga0.55Sb vertical tunnel FETs","authors":"Guangle Zhou, Y. Lu, R. Li, Q. Zhang, W. Hwang, Q. Liu, T. Vasen, H. Zhu, J. Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing","doi":"10.1109/DRC.2011.5994499","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994499","url":null,"abstract":"Tunnel field-effect transistors (TFETs) are under intense investigation for low-power applications because of their potential for extremely low subthreshold swing (SS) and low off-state leakage [1]. III–V semiconductors with small effective mass and near broken band alignment are considered to be ideal for TFETs in that they promise high on-current and I<inf>ON</inf>/I<inf>OFF</inf> ratios [2–3]. In this paper, we report the first demonstration of an InAs/Al<inf>0.45</inf>Ga<inf>0.55</inf>Sb heterojunction TFETs fabricated using an optical-lithography-only, self-aligned process and also investigate the effects limiting the InAs/Al<inf>0.45</inf>Ga<inf>0.55</inf>Sb TFET performance.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994451
Tae-Sun Lim, D. Jain, P. Burke
Although naturally occurring biological nanopores have shortcomings such as a relatively weak structural durability and a limited life-time, they are still intriguing candidates for nanobiosensing applications due to their sensitivity and specificity to analytes as well as various choices of ion channels depending on functionalities. In order to overcome limitations of biological nanopores, man-made solid-state nanopores have been explored. The fabricated solid-state nanopore is structurally durable and suitable for nanofabrication process yet it is still challenging to construct and a low throughput process, and lacks the chemical specificity of natural ion channels[1]. Can bionanotechnology be applied to improve this situation? Recent work has shown that nanomaterials (nanotubes, nanowires) can be gated by electrolyte, and even coated with lipid bilayers allowing charges of either the bilayer themselves[2]. These reports focus on time average changes in source/drain current due to gating by charges near the nanowire/nanotube. Thus, to date, no nanowire/nanotube device has been able to measure the time-dependent single ion channel recording.
{"title":"Protein nanopore-gated bio-transistor for membrane ionic current recording","authors":"Tae-Sun Lim, D. Jain, P. Burke","doi":"10.1109/DRC.2011.5994451","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994451","url":null,"abstract":"Although naturally occurring biological nanopores have shortcomings such as a relatively weak structural durability and a limited life-time, they are still intriguing candidates for nanobiosensing applications due to their sensitivity and specificity to analytes as well as various choices of ion channels depending on functionalities. In order to overcome limitations of biological nanopores, man-made solid-state nanopores have been explored. The fabricated solid-state nanopore is structurally durable and suitable for nanofabrication process yet it is still challenging to construct and a low throughput process, and lacks the chemical specificity of natural ion channels[1]. Can bionanotechnology be applied to improve this situation? Recent work has shown that nanomaterials (nanotubes, nanowires) can be gated by electrolyte, and even coated with lipid bilayers allowing charges of either the bilayer themselves[2]. These reports focus on time average changes in source/drain current due to gating by charges near the nanowire/nanotube. Thus, to date, no nanowire/nanotube device has been able to measure the time-dependent single ion channel recording.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126099625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994404
S. Steiger, M. Povolotskyi, Hong-hyun Park, T. Kubis, G. Hegde, B. Haley, M. Rodwell, Gerhard Klimeck
Modeling and simulation take an important role in the exploration and design optimization of novel devices. As the downscaling of electronic devices continues, the description of interfaces, randomness, and disorder on an atomistic level gains importance and continuum descriptions lose their validity. Often a full-band description of the electronic structure is needed to model the interaction of different valleys and nonparabolicity effects. NEMO 5 [1] is a modeling tool that addresses these issues and is able to provide insight into a broad range of devices. It unifies the capabilities of prior projects: multiscale approaches to quantum transport in planar structures in NEMO-1D [2], multimillion-atom simulations of strain and electronic structure in NEMO-3D [3] and NEMO-3D-Peta [4], and quantum transport in nonplanar structures in OMEN [5]. NEMO 5 aims at becoming a community code whose structure, implementation, resource requirements and license allow experimental and theoretical researchers in academia and industry alike to use and extend the tool.
{"title":"The nanoelectronic modeling tool NEMO 5: Capabilities, validation, and application to Sb-heterostructures","authors":"S. Steiger, M. Povolotskyi, Hong-hyun Park, T. Kubis, G. Hegde, B. Haley, M. Rodwell, Gerhard Klimeck","doi":"10.1109/DRC.2011.5994404","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994404","url":null,"abstract":"Modeling and simulation take an important role in the exploration and design optimization of novel devices. As the downscaling of electronic devices continues, the description of interfaces, randomness, and disorder on an atomistic level gains importance and continuum descriptions lose their validity. Often a full-band description of the electronic structure is needed to model the interaction of different valleys and nonparabolicity effects. NEMO 5 [1] is a modeling tool that addresses these issues and is able to provide insight into a broad range of devices. It unifies the capabilities of prior projects: multiscale approaches to quantum transport in planar structures in NEMO-1D [2], multimillion-atom simulations of strain and electronic structure in NEMO-3D [3] and NEMO-3D-Peta [4], and quantum transport in nonplanar structures in OMEN [5]. NEMO 5 aims at becoming a community code whose structure, implementation, resource requirements and license allow experimental and theoretical researchers in academia and industry alike to use and extend the tool.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994405
A. Agrawal, A. Ali, R. Misra, P. Schiffer, B. R. Bennett, J. B. Boos, S. Datta
Antimonide based compound semiconductors have gained considerable interest in recent years due to their superior electron and hole transport properties [1]. A Mixed anion InAsySb1−y quantum well heterostructure with high electron mobility of 13,300 cm2/Vs has already been demonstrated at a sheet carrier density of 2×1012 /cm2, albeit for a thick EOT quantum well (QW) structure [2]. A thin EOT structure is desired for improving short channel effects while maintaining the high electron mobility in the QW. In this paper, we study the low field electron transport properties in the high mobility InAs0.8Sb0.2 quantum well as we scale the QW heterostructure. Fig. 1(a),(b) show the schematic of the thick (TQW=12nm) and scaled (TQW=7.5nm) quantum well FET structure using InAs0.8Sb0.2 as channel material, In0.2Al0.8Sb barrier layer and an ultra-thin GaSb surface layer for avoiding surface oxidation of Al in the barrier [2]. Fig. 2(a),(b) show the simulated energy band diagram of the two structures using self-consistent Schrodinger-Poisson simulation, indicating strong electron confinement in the QW. The effect of nonparabolicity on thick QW with TQW=12nm has already been studied and an effective mass (m*) of 0.043m0 has been extracted experimentally [3]. For scaled QW the subband spacing was adjusted in order to achieve electron sheet charge density as a function of temperature, and the extracted density of states m*=0.05m0 was correlated to the transport effective mass. Experimental work to verify the obtained effective mass for scaled QW is underway.
{"title":"Experimental determination of dominant scattering mechanisms in scaled InAsSb quantum well","authors":"A. Agrawal, A. Ali, R. Misra, P. Schiffer, B. R. Bennett, J. B. Boos, S. Datta","doi":"10.1109/DRC.2011.5994405","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994405","url":null,"abstract":"Antimonide based compound semiconductors have gained considerable interest in recent years due to their superior electron and hole transport properties [1]. A Mixed anion InAs<inf>y</inf>Sb<inf>1−y</inf> quantum well heterostructure with high electron mobility of 13,300 cm<sup>2</sup>/Vs has already been demonstrated at a sheet carrier density of 2×10<sup>12</sup> /cm<sup>2</sup>, albeit for a thick EOT quantum well (QW) structure [2]. A thin EOT structure is desired for improving short channel effects while maintaining the high electron mobility in the QW. In this paper, we study the low field electron transport properties in the high mobility InAs<inf>0.8</inf>Sb<inf>0.2</inf> quantum well as we scale the QW heterostructure. Fig. 1(a),(b) show the schematic of the thick (T<inf>QW</inf>=12nm) and scaled (T<inf>QW</inf>=7.5nm) quantum well FET structure using InAs<inf>0.8</inf>Sb<inf>0.2</inf> as channel material, In<inf>0.2</inf>Al<inf>0.8</inf>Sb barrier layer and an ultra-thin GaSb surface layer for avoiding surface oxidation of Al in the barrier [2]. Fig. 2(a),(b) show the simulated energy band diagram of the two structures using self-consistent Schrodinger-Poisson simulation, indicating strong electron confinement in the QW. The effect of nonparabolicity on thick QW with T<inf>QW</inf>=12nm has already been studied and an effective mass (m*) of 0.043m<inf>0</inf> has been extracted experimentally [3]. For scaled QW the subband spacing was adjusted in order to achieve electron sheet charge density as a function of temperature, and the extracted density of states m*=0.05m<inf>0</inf> was correlated to the transport effective mass. Experimental work to verify the obtained effective mass for scaled QW is underway.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129852257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-20DOI: 10.1109/DRC.2011.5994436
K. Storm, G. Nylund, M. Borgstrom, J. Wallentin, C. Fasth, C. Thelander, L. Samuelson
Semiconducting nanowires (NWs) constitute an interesting platform as building blocks for various types of devices as well as for studies of fundamental material transport properties in one dimension. Nanowires have many interesting properties, such as the ability to incorporate strongly lattice-mismatched material combinations along its axis due to radial relaxation of interface strain. Furthermore, its inherent cylindrical geometry makes it an ideal candidate for devices implementing gates wrapped around the nanowire channel; the optimal geometry for maximum gate to channel coupling.
{"title":"Creating dynamic nanowire devices using wrapped gates","authors":"K. Storm, G. Nylund, M. Borgstrom, J. Wallentin, C. Fasth, C. Thelander, L. Samuelson","doi":"10.1109/DRC.2011.5994436","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994436","url":null,"abstract":"Semiconducting nanowires (NWs) constitute an interesting platform as building blocks for various types of devices as well as for studies of fundamental material transport properties in one dimension. Nanowires have many interesting properties, such as the ability to incorporate strongly lattice-mismatched material combinations along its axis due to radial relaxation of interface strain. Furthermore, its inherent cylindrical geometry makes it an ideal candidate for devices implementing gates wrapped around the nanowire channel; the optimal geometry for maximum gate to channel coupling.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128033938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：