Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes

Abstract

Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. With the end of happy scaling era, change of device architecture has raised integration complexity along with several sort channel effects, mobility degradation, variability and quantum tunneling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7nm technology nodes. Towards low power and high speed (More-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the question of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass the FinFETs. In this work, we use 3-D predictive simulations to study the performance potential of SNS-FETs at 3nm technology node.