{"title":"Near threshold RF-only analog to digital converter","authors":"P. Gadfort, P. Franzon","doi":"10.1109/SUBVT.2012.6404321","DOIUrl":null,"url":null,"abstract":"This paper describes an analog-to-digital converter (ADC) capable of operating in a RF-only circuit topology. A major limitation to direct RF-powered sensors are the lack of analog circuits. The proposed architecture is comprised of a cross-coupled pair of inverters, which act as the comparator for the ADC. This setup has been simulated in IBMs 0.13 μm bulk CMOS process for a 3 bit analog-to-digital converter (ADC). At a RF supply voltage of 300 mVRMS and frequency 13.57 MHz, the ADC has a resolution of 20 mV and can resolve voltages ranging from -80 mV to 80 mV, and at a frequency of 915 MHz the ADC can resolve voltages ranging from -140 mV to 140 mV. In order to optimize the ADC operation, the sampling time has been adjusted to one-third of the evaluation time, to give the comparator enough time to complete the amplification.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SUBVT.2012.6404321","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes an analog-to-digital converter (ADC) capable of operating in a RF-only circuit topology. A major limitation to direct RF-powered sensors are the lack of analog circuits. The proposed architecture is comprised of a cross-coupled pair of inverters, which act as the comparator for the ADC. This setup has been simulated in IBMs 0.13 μm bulk CMOS process for a 3 bit analog-to-digital converter (ADC). At a RF supply voltage of 300 mVRMS and frequency 13.57 MHz, the ADC has a resolution of 20 mV and can resolve voltages ranging from -80 mV to 80 mV, and at a frequency of 915 MHz the ADC can resolve voltages ranging from -140 mV to 140 mV. In order to optimize the ADC operation, the sampling time has been adjusted to one-third of the evaluation time, to give the comparator enough time to complete the amplification.